•VLSI Design I; A. Milenkovic •1CPE/EE 427, CPE 527 VLSI Design IL17: Power and Designing for Low PowerDepartment of Electrical and Computer Engineering University of Alabama in HuntsvilleAleksandar Milenkovic ( www.ece.uah.edu/~milenka )www.ece.uah.edu/~milenka/cpe527-05F10/24/2005 VLSI Design I; A. Milenkovic 2Review: Why Power Matters• Packaging costs• Power supply rail design• Chip and system cooling costs• Noise immunity and system reliability• Battery life (in portable systems)• Environmental concerns– Office equipment accounted for 5% of total US commercial energy usage in 1993– Energy Star compliant systems10/24/2005 VLSI Design I; A. Milenkovic 3Review: CMOS Energy & Power EquationsE = CLVDD2 P0→1+ tscVDDIpeakP0→1 + VDDIleakageP = CLVDD2f0→1+ tscVDDIpeakf0→1 + VDDIleakageDynamic powerShort-circuit powerLeakage powerf0→1= P0→1* fclock10/24/2005 VLSI Design I; A. Milenkovic 4Dynamic Power ConsumptionEnergy/transition = CL * VDD2 * P0→1Pdyn= Energy/transition * f = CL* VDD2 * P0→1* fPdyn= CEFF* VDD2* f where CEFF= P0→1CLNot a function of transistor sizes!Data dependent - a function of switching activity!Vin VoutCLVddf0→110/24/2005 VLSI Design I; A. Milenkovic 5Lowering Dynamic PowerPdyn= CLVDD2P0→1 fCapacitance:Function of fan-out, wire length, transistor sizesSupply Voltage:Has been dropping with successive generationsClock frequency:Increasing…Activity factor:How often, on average, do wires switch?10/24/2005 VLSI Design I; A. Milenkovic 6Short Circuit Power ConsumptionFinite slope of the input signal causes a direct current path between VDDand GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting.Vin VoutCLIsc•VLSI Design I; A. Milenkovic •210/24/2005 VLSI Design I; A. Milenkovic 7Short Circuit Currents Determinates• Duration and slope of the input signal, tsc•Ipeakdetermined by – the saturation current of the P and N transistors which depend on their sizes, process technology, temperature, etc.– strong function of the ratio between input and output slopes• a function of CLEsc= tscVDDIpeakP0→1Psc= tscVDDIpeakf0→110/24/2005 VLSI Design I; A. Milenkovic 8Impact of CLon PscVin VoutCLIsc≈ 0Vin VoutCLIsc≈ ImaxLarge capacitive loadOutput fall time significantly larger than input rise time.Small capacitive loadOutput fall time substantially smaller than the input rise time.10/24/2005 VLSI Design I; A. Milenkovic 9Ipeakas a Function of CL-0.500.511.522.50246Ipeak(A)time (sec)x 10-10x 10-4CL= 20 fFCL= 100 fFCL= 500 fF500 psec input slopeShort circuit dissipation is minimized by matching the rise/fall times of the input and output signals - slope engineering.When load capacitance is small, Ipeakis large.10/24/2005 VLSI Design I; A. Milenkovic 10Pscas a Function of Rise/Fall Times012345678024P normalizedtsin/tsoutVDD= 3.3 VVDD= 2.5 VVDD= 1.5Vnormalized wrt zero input rise-time dissipationWhen load capacitance is small (tsin/tsout> 2 for VDD > 2V) the power is dominated by PscIf VDD< VTn+ |VTp| then Pscis eliminated since both devices are never on at the same time.W/Lp= 1.125 µm/0.25 µmW/Ln= 0.375 µm/0.25 µmCL= 30 fF10/24/2005 VLSI Design I; A. Milenkovic 11Leakage (Static) Power ConsumptionSub-threshold current is the dominant factor.All increase exponentially with temperature!VDDIleakageVoutDrain junction leakageSub-threshold currentGate leakage10/24/2005 VLSI Design I; A. Milenkovic 12Leakage as a Function of VT0 0.2 0.4 0.6 0.8 1VGS (V)ID (A)VT=0.4VVT=0.1V10-210-1210-7 Continued scaling of supply voltage and the subsequent scaling of threshold voltage will make subthresholdconduction a dominant component of power dissipation. An 90mV/decade VTroll-off - so each 255mV increase in VTgives 3 orders of magnitude reduction in leakage (but adversely affects performance)•VLSI Design I; A. Milenkovic •310/24/2005 VLSI Design I; A. Milenkovic 13TSMC Processes Leakage and VT800.25 V13,000920/4000.08 µm 24 Å1.2 VCL013 HS520.29 V1,800860/3700.11 µm 29 Å1.5 VCL015 HS42 Å42 Å42 Å42 ÅTox(effective)43142230FET Perf. (GHz)0.40 V0.73 V0.63 V0.42 VVTn3000.151.6020Ioff(leakage) (ρA/µm)780/360320/130500/180600/260IDSat(n/p) (µA/µm)0.13 µm 0.18 µm 0.16 µm 0.16 µm Lgate2 V1.8 V1.8 V1.8 VVddCL018 HSCL018 ULPCL018 LPCL018 GFrom MPR, 200010/24/2005 VLSI Design I; A. Milenkovic 14Exponential Increase in Leakage Currents11010010001000030 40 50 60 70 80 90 100 1100.250.180.130.1Temp(C)Ileakage(nA/µm)From De,199910/24/2005 VLSI Design I; A. Milenkovic 15Review: Energy & Power EquationsE = CLVDD2 P0→1+ tscVDDIpeakP0→1 + VDDIleakageP = CLVDD2f0→1+ tscVDDIpeakf0→1 + VDDIleakageDynamic power(~90% today and decreasing relatively)Short-circuit power(~8% today and decreasing absolutely)Leakage power(~2% today and increasing)f0→1= P0→1* fclock10/24/2005 VLSI Design I; A. Milenkovic 16Power and Energy Design Space+ Variable VTSleep TransistorsMulti-VddVariable VT+ Multi-VTLeakageDFS, DVS(Dynamic Freq, Voltage Scaling)Clock GatingLogic DesignReduced VddSizingMulti-VddActiveRun TimeNon-active ModulesDesign TimeEnergy Variable Throughput/LatencyConstant Throughput/Latency10/24/2005 VLSI Design I; A. Milenkovic 17Dynamic Power as a Function of Device Size• Device sizing affects dynamic energy consumption– gain is largest for networks with large overall effective fan-outs (F = CL/Cg,1)• The optimal gate sizing factor (f) for dynamic energy is smaller than the one for performance, especially for large F’s– e.g., for F=20, fopt(energy) = 3.53 while fopt(performance) = 4.47• If energy is a concern avoid oversizing beyond the optimal1 2 3 4 5 6 700.511.5fnormalized energyF=1F=2F=5F=10F=20From Nikolic, UCB10/24/2005 VLSI Design I; A. Milenkovic 18Dynamic Power Consumption is Data Dependent011001010100OutBA2-input NOR GateWith input signal probabilitiesPA=1 = 1/2PB=1 = 1/2Static transition probabilityP0→1 = Pout=0 x Pout=1= P0x (1-P0)• Switching activity, P0→1, has two components– A static component – function of the logic topology– A dynamic component – function of the timing behavior (glitching)NOR static transition probability= 3/4 x 1/4 = 3/16•VLSI Design I; A. Milenkovic •410/24/2005 VLSI Design I; A. Milenkovic 19NOR Gate Transition ProbabilitiesCLABBAP0→1 = P0 x P1= (1-(1-PA)(1-PB)) (1-PA)(1-PB)PAPB010 1• Switching activity is a strong function of the input signal