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UAH CPE 427 - Logical Effort

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CPE EE 427 CPE 527 VLSI Design I L10 Logical Effort Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic www ece uah edu milenka www ece uah edu milenka cpe527 05F Course Administration Instructor URL TA Labs Project Test I Text Review Today 9 20 2005 VLSI Design I A Milenkovic Aleksandar Milenkovic milenka ece uah edu www ece uah edu milenka EB 217 L Mon 5 30 PM 6 30 PM Wen 12 30 13 30 PM http www ece uah edu milenka cpe527 05F Joel Wilder Lab 3 due 10 07 05 Proposals due 10 10 05 10 12 05 CMOS VLSI Design 3rd ed Weste Harris Chapters 1 2 3 4 Logical Effort Chapter 4 VLSI Design I A Milenkovic 2 1 Outline Introduction Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary 9 20 2005 VLSI Design I A Milenkovic 3 Introduction Chip designers face a bewildering array of choices What is the best circuit topology for a function How many stages of logic give least delay How wide should the transistors be Logical effort is a method to make these decisions Uses a simple model of delay Allows back of the envelope calculations Helps make rapid comparisons between alternatives Emphasizes remarkable symmetries 9 20 2005 VLSI Design I A Milenkovic VLSI Design I A Milenkovic 4 2 Example Ben Bitdiddle is the memory designer for the Motoroil 68W86 an embedded automotive processor Help Ben design the decoder for a register file A 3 0 A 3 0 32 bits 16 16 word register file Each word is 32 bits wide Each bit presents load of 3 unit sized transistors True and complementary address inputs A 3 0 Each input may drive 10 unit sized transistors Register File 16 words Decoder specifications 4 16 Decoder Ben needs to decide How many stages to use How large should each gate be How fast can decoder operate 9 20 2005 VLSI Design I A Milenkovic 5 Delay in a Logic Gate Express delays in process independent unit d 9 20 2005 VLSI Design I A Milenkovic d abs 3RC 12 ps in 180 nm process 40 ps in 0 6 m process VLSI Design I A Milenkovic 6 3 Delay in a Logic Gate Express delays in process independent unit d d abs Delay has two components d f p 9 20 2005 VLSI Design I A Milenkovic 7 Delay in a Logic Gate Express delays in process independent unit d d abs Delay has two components d f p Effort delay f gh a k a stage effort Again has two components 9 20 2005 VLSI Design I A Milenkovic VLSI Design I A Milenkovic 8 4 Delay in a Logic Gate Express delays in process independent unit d d abs Delay has two components d f p Effort delay f gh a k a stage effort Again has two components g logical effort Measures relative ability of gate to deliver current g 1 for inverter 9 20 2005 VLSI Design I A Milenkovic 9 Delay in a Logic Gate Express delays in process independent unit d d abs Delay has two components d f p Effort delay f gh a k a stage effort Again has two components h electrical effort Cout Cin Ratio of output to input capacitance Sometimes called fanout 9 20 2005 VLSI Design I A Milenkovic VLSI Design I A Milenkovic 10 5 Delay in a Logic Gate Express delays in process independent unit d d abs Delay has two components d f p Parasitic delay p Represents delay of gate driving no load Set by internal parasitic capacitance 9 20 2005 VLSI Design I A Milenkovic 11 Delay Plots d f p 2 input NAND gh p NormalizedDelay d 6 Inverter g p d 5 g p d 4 3 2 1 0 0 1 2 3 4 5 ElectricalEffort h Cout Cin 9 20 2005 VLSI Design I A Milenkovic VLSI Design I A Milenkovic 12 6 Delay Plots d f p 2 input NAND gh p NormalizedDelay d 6 What about NOR2 Inverter g 4 3 p 2 d 4 3 h 2 5 3 g 1 p 1 d h 1 2 EffortDelay f 4 1 Parasitic Delay p 0 0 1 2 3 4 5 ElectricalEffort h Cout Cin 9 20 2005 VLSI Design I A Milenkovic 13 Computing Logical Effort DEF Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current Measure from delay vs fanout plots Or estimate by counting transistor widths 2 A Y 1 Cin 3 g 3 3 9 20 2005 VLSI Design I A Milenkovic 2 Y 2 A 2 B 2 A 4 B 4 Cin 4 g 4 3 VLSI Design I A Milenkovic Y 1 1 Cin 5 g 5 3 14 7 Catalog of Gates Logical effort of common gates Gate type Number of inputs 1 2 3 4 n NAND 4 3 5 3 6 3 n 2 3 NOR 5 3 7 3 9 3 2n 1 3 2 2 2 2 4 4 6 12 6 8 16 16 8 Inverter Tristate mux 1 2 XOR XNOR 9 20 2005 VLSI Design I A Milenkovic 15 Catalog of Gates Parasitic delay of common gates In multiples of pinv 1 Gate type Number of inputs 1 2 3 4 n NAND 2 3 4 n NOR 2 3 4 n 4 6 8 2n 4 6 8 Inverter Tristate mux XOR XNOR 9 20 2005 VLSI Design I A Milenkovic 1 2 VLSI Design I A Milenkovic 16 8 Example Ring Oscillator Estimate the frequency of an N stage ring oscillator Logical Effort g Electrical Effort h Parasitic Delay p Stage Delay d Frequency fosc 9 20 2005 VLSI Design I A Milenkovic 17 Example Ring Oscillator Estimate the frequency of an N stage ring oscillator 31 stage ring oscillator in Logical Effort g 1 0 6 m process has frequency of 200 MHz Electrical Effort h 1 Parasitic Delay p 1 Stage Delay d 2 Frequency fosc 1 2 N d 1 4N 9 20 2005 VLSI Design I A Milenkovic VLSI Design I A Milenkovic 18 9 Example FO4 Inverter Estimate the delay of a fanout of 4 FO4 inverter d Logical Effort g Electrical Effort Parasitic Delay Stage Delay d 9 20 2005 h p VLSI Design I A Milenkovic 19 Example FO4 Inverter Estimate the delay of a fanout of 4 FO4 inverter d Logical Effort g 1 Electrical Effort h 4 Parasitic Delay p 1 Stage Delay d 5 9 20 2005 VLSI Design I A Milenkovic The FO4 delay is about 200 ps in 0 6 m process 60 ps in a 180 nm process f 3 ns in an f m process VLSI Design I A Milenkovic 20 10 Multistage Logic Networks Logical effort generalizes to multistage networks Path Logical Effort G gi Path Electrical Effort g1 1 h1 x 10 9 20 2005 Cout path Cin path F f i gi …


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