•VLSI Design I; A. Milenkovic •1CPE/EE 427, CPE 527 VLSI Design IL18: Circuit FamiliesDepartment of Electrical and Computer Engineering University of Alabama in HuntsvilleAleksandar Milenkovic ( www.ece.uah.edu/~milenka )www.ece.uah.edu/~milenka/cpe527-05F10/24/2005 VLSI Design I; A. Milenkovic 2Outline• Pseudo-nMOS Logic• Dynamic Logic• Pass Transistor Logic10/24/2005 VLSI Design I; A. Milenkovic 3Introduction• What makes a circuit fast?– I = C dV/dt -> tpd∝ (C/I) ∆V– low capacitance–high current– small swing• Logical effort is proportional to C/I• pMOS are the enemy!– High capacitance for a given current• Can we take the pMOS capacitance off the input?• Various circuit families try to do this…BA1144Y10/24/2005 VLSI Design I; A. Milenkovic 4Pseudo-nMOS• In the old days, nMOS processes had no pMOS– Instead, use pull-up transistor that is always ON• In CMOS, use a pMOS that is always ON– Ratio issue– Make pMOS about ¼ effective strength of pulldown networkVoutVin16/2P/2Idsload0 0.3 0.6 0.9 1.2 1.5 1.800.30.60.91.21.51.8P = 24P = 4P = 14VinVout10/24/2005 VLSI Design I; A. Milenkovic 5Pseudo-nMOS Gates• Design for unit current on outputto compare with unit inverter.• pMOS fights nMOSInverter NAND2 NOR2AYBAYABgu =gd =gavg =pu =pd =pavg =Ygu =gd =gavg =pu =pd =pavg =gu =gd =gavg =pu =pd =pavg =finputsY10/24/2005 VLSI Design I; A. Milenkovic 6Pseudo-nMOS Gates• Design for unit current on outputto compare with unit inverter.• pMOS fights nMOSInverter NAND2 NOR24/32/3AY8/38/32/3BAYAB4/34/32/3gu =gd =gavg =pu =pd =pavg =Ygu =gd =gavg =pu =pd =pavg =gu =gd =gavg =pu =pd =pavg =finputsY•VLSI Design I; A. Milenkovic •210/24/2005 VLSI Design I; A. Milenkovic 7Pseudo-nMOS Gates• Design for unit current on outputto compare with unit inverter.• pMOS fights nMOSInverter NAND2 NOR24/32/3AY8/38/32/3BAYAB4/34/32/3gu = 4/3gd = 4/9gavg = 8/9pu =pd =pavg =Ygu = 8/3gd = 8/9gavg = 16/9pu =pd =pavg =gu = 4/3gd = 4/9gavg = 8/9pu =pd =pavg =finputsY10/24/2005 VLSI Design I; A. Milenkovic 8Pseudo-nMOS Gates• Design for unit current on outputto compare with unit inverter.• pMOS fights nMOSInverter NAND2 NOR24/32/3AY8/38/32/3BAYAB4/34/32/3gu = 4/3gd = 4/9gavg = 8/9pu = 6/3pd = 6/9pavg = 12/9Ygu = 8/3gd = 8/9gavg = 16/9pu = 10/3pd = 10/9pavg = 20/9gu = 4/3gd = 4/9gavg = 8/9pu = 10/3pd = 10/9pavg = 20/9finputsY10/24/2005 VLSI Design I; A. Milenkovic 9Pseudo-nMOS Design• Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H•G = •F =•P =•N =•D =In1InkYPseudo-nMOS11H10/24/2005 VLSI Design I; A. Milenkovic 10Pseudo-nMOS Design• Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H• G = 1 * 8/9 = 8/9• F = GBH = 8H/9• P = 1 + (4+8k)/9 = (8k+13)/9•N = 2•D = NF1/N+ P = In1InkYPseudo-nMOS11H42 8 1339Hk++10/24/2005 VLSI Design I; A. Milenkovic 11Pseudo-nMOS Power• Pseudo-nMOS draws power whenever Y = 0– Called static power P = I•VDD– A few mA / gate * 1M gates would be a problem– This is why nMOS went extinct!• Use pseudo-nMOS sparingly for wide NORs• Turn off pMOS when not in useABYCen10/24/2005 VLSI Design I; A. Milenkovic 12Dynamic Logic• Dynamic gates uses a clocked pMOS pullup• Two modes: precharge and evaluate12AY4/32/3AY11AYφStatic Pseudo-nMOS Dynamicφ Precharge EvaluateYPrecharge•VLSI Design I; A. Milenkovic •310/24/2005 VLSI Design I; A. Milenkovic 13The Foot• What if pulldown network is ON during precharge?• Use series evaluation transistor to prevent fight.AYφfootprecharge transistorφYinputsφYinputsfooted unfootedff10/24/2005 VLSI Design I; A. Milenkovic 14Logical EffortInverter NAND2 NOR211AY221BAYAB111gd =pd =gd =pd =gd =pd =Yφφφ21AY331BAYAB221gd =pd =gd =pd =gd =pd =Yφφφfootedunfooted32210/24/2005 VLSI Design I; A. Milenkovic 15Logical EffortInverter NAND2 NOR211AY221BAYAB111gd = 1/3pd = 2/3gd = 2/3pd = 3/3gd = 1/3pd = 3/3Yφφφ21AY331BAYAB221gd = 2/3pd = 3/3gd = 3/3pd = 4/3gd = 2/3pd = 5/3Yφφφfootedunfooted32210/24/2005 VLSI Design I; A. Milenkovic 16Monotonicity• Dynamic gates require monotonically rising inputs during evaluation–0 -> 0–0 -> 1–1 -> 1– But not 1 -> 0φ Precharge EvaluateYPrechargeAOutput should rise but does notviolates monotonicity during evaluationAφ10/24/2005 VLSI Design I; A. Milenkovic 17Monotonicity Woes• But dynamic gates produce monotonically falling outputs during evaluation• Illegal for one dynamic gate to drive another!AXφYφ Precharge EvaluateXPrechargeA = 1Y10/24/2005 VLSI Design I; A. Milenkovic 18Monotonicity Woes• But dynamic gates produce monotonically falling outputs during evaluation• Illegal for one dynamic gate to drive another!AXφYφ Precharge EvaluateXPrechargeA = 1Y should rise but cannotYX monotonically falls during evaluation•VLSI Design I; A. Milenkovic •410/24/2005 VLSI Design I; A. Milenkovic 19Domino Gates• Follow dynamic stage with inverting static gate– Dynamic / static pair is called domino gate– Produces monotonic outputsφ Precharge EvaluateWPrechargeXYZAφBCφφφCABWXYZ=XZHHAWφB CXYZdomino ANDdynamicNANDstaticinverter10/24/2005 VLSI Design I; A. Milenkovic 20Domino Optimizations• Each domino gate triggers next one, like a string of dominos toppling over• Gates evaluate sequentially but precharge in parallel• Thus evaluation is more critical than precharge• HI-skewed static stages can perform logicS0D0S1D1S2D2S3D3φS4D4S5D5S6D6S7D7φYH10/24/2005 VLSI Design I; A. Milenkovic 21Dual-Rail Domino• Domino only performs noninverting functions:– AND, OR but not NAND, NOR, or XOR• Dual-rail domino solves this problem– Takes true and complementary inputs – Produces true and complementary outputsinvalid11‘1’01‘0’10Precharged00Meaningsig_lsig_hY_hfφφinputsY_lf10/24/2005 VLSI Design I; A. Milenkovic 22Example: AND/NAND• Given A_h, A_l, B_h, B_l• Compute Y_h = A * B, Y_l = ~(A * B)10/24/2005 VLSI Design I; A. Milenkovic 23Example: AND/NAND• Given A_h, A_l, B_h, B_l• Compute Y_h = A * B, Y_l = ~(A * B)• Pulldown networks are conduction complementsY_hφφY_lA_hB_hB_lA_l= A*B= A*B10/24/2005 VLSI Design I; A. Milenkovic 24Example: XOR/XNOR•