CPE/EE 427, CPE 527 VLSI Design IDelay EstimationReview: CMOS Circuit StylesReview: Static Complementary CMOSReview: OAI22 Logic GraphReview: OAI22 LayoutReview: VTC is Data-DependentStatic CMOS Full Adder CircuitStatic CMOS Full Adder CircuitTransient ResponseInverter Step ResponseInverter Step ResponseInverter Step ResponseInverter Step ResponseInverter Step ResponseInverter Step ResponseDelay DefinitionsDelay DefinitionsDelay DefinitionsSimulated Inverter DelayDelay EstimationRC Delay ModelsExample: 3-input NANDExample: 3-input NANDExample: 3-input NAND3-input NAND Caps3-input NAND Caps3-input NAND CapsElmore DelayExample: 2-input NANDExample: 2-input NANDExample: 2-input NANDExample: 2-input NANDExample: 2-input NANDExample: 2-input NANDExample: 2-input NANDDelay ComponentsContamination DelayDiffusion CapacitanceLayout ComparisonCPE/EE 427, CPE 527 VLSI Design IDelay EstimationDepartment of Electrical and Computer Engineering University of Alabama in Huntsvillewww.ece.uah.edu/~milenkaAleksandar Milenkovic ( )9/20/2006 VLSI Design I; A. Milenkovic 2Review: CMOS Circuit Styles• Static complementary CMOS - except during switching, output connected to either VDD or GND via a low-resistance path– high noise margins• full rail to rail swing• VOH and VOL are at VDD and GND, respectively– low output impedance, high input impedance– no steady state path between VDD and GND (no static power consumption)– delay a function of load capacitance and transistor resistance– comparable rise and fall times (under the appropriate transistorsizing conditions)• Dynamic CMOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes– simpler, faster gates– increased sensitivity to noise9/20/2006 VLSI Design I; A. Milenkovic 3Review: Static Complementary CMOSPull-up network (PUN) and pull-down network (PDN)VDDF(In1,In2,…InN)In1PUNPDN……PMOS transistors onlypull-up: make a connection from VDDto F when F(In1,In2,…InN) = 1NMOS transistors onlypull-down: make a connection from F to GND when F(In1,In2,…InN) = 0In2InNIn1In2InNPUN and PDN are dual logic networks9/20/2006 VLSI Design I; A. Milenkovic 4Review: OAI22 Logic GraphCABX = !((A+B)•(C+D))BADXABPUNCCDVDDXDPDNABCDGND9/20/2006 VLSI Design I; A. Milenkovic 5Review: OAI22 LayoutBADCVDDXGND Some functions have no consistent Euler path like x = !(a + bc + de) (but x = !(bc + a + de) does!)9/20/2006 VLSI Design I; A. Milenkovic 6Review: VTC is Data-DependentABF= A • BABM1M2M3M4VGS2= VA –VDS1CintVGS1= VB0123012A,B: 0 -> 1B=1, A:0 -> 1A=1, B:0->10.5µ/0.25µ NMOS0.75µ /0.25µ PMOS The threshold voltage of M2is higher than M1due to the body effect (γ)VTn2= VTn0+ γ(√(|2φF| + Vint) - √|2φF|)since VSBof M2is not zero (when VB= 0) due to the presence of CintVTn1= VTn0DDSSweakerPUN9/20/2006 VLSI Design I; A. Milenkovic 7Static CMOS Full Adder CircuitBBBBBBBBAAAAAAAACinCinCinCinCin!Cout!Sum9/20/2006 VLSI Design I; A. Milenkovic 8Static CMOS Full Adder CircuitBBBBBBBBAAAAAAAACinCinCinCinCin!Cout!Sum!Cout= !Cin& (!A | !B) | (!A & !B)Cout= Cin& (A | B) | (A & B)!Sum = Cout& (!A | !B | !Cin) | (!A & !B & !CSum = !Cout& (A | B | Cin) | (A & B & Cin)in)9/20/2006 VLSI Design I; A. Milenkovic 9Transient Response• DC analysis tells us Voutif Vinis constant• Transient analysis tells us Vout(t) if Vin(t) changes– Requires solving differential equations• Input is usually considered to be a step or ramp– From 0 to VDD or vice versa9/20/2006 VLSI Design I; A. Milenkovic 10Inverter Step Response• Ex: find step response of inverter driving load capVin(t)Vout(t)CloadIdsn(t)0()())(oiutnoutVtttVtVddt=<==9/20/2006 VLSI Design I; A. Milenkovic 11Inverter Step Response• Ex: find step response of inverter driving load capVin(t)Vout(t)CloadIdsn(t)00()()()()ouDDintoutut t VddtttVtVVt==<−=9/20/2006 VLSI Design I; A. Milenkovic 12Inverter Step Response• Ex: find step response of inverter driving load capVin(t)Vout(t)CloadIdsn(t)00(())(())DDDoiDotnutuVtut t VVddttVVtt=−=<=9/20/2006 VLSI Design I; A. Milenkovic 13Inverter Step Response• Ex: find step response of inverter driving load cap00()()()(())DDDDloadouidtonut snVVut t VttVtVddt CtIt=−==−<Vin(t)Vout(t)CloadIdsn(t)0()DDtoutoudstDDtnIt VVVV VVtt≤⎧⎪=>−⎨⎪<−⎩9/20/2006 VLSI Design I; A. Milenkovic 14Inverter Step Response• Ex: find step response of inverter driving load cap00()()()(())DDDDloadouidtonut snVVut t VttVtVddt CtIt=−==−<()02202))(()(DDDDtDDoutoutout outDtntdsDI VttVV VVVV VVVtVtVtββ⎧≤⎪⎪=− >−⎨⎪⎛⎞−− < −⎪⎜⎟⎝⎠⎩Vin(t)Vout(t)CloadIdsn(t)9/20/2006 VLSI Design I; A. Milenkovic 15Inverter Step Response• Ex: find step response of inverter driving load cap00()()()(())DDDDloadouidtonut snVVut t VttVtVddt CtIt=−==−<()02202))(()(DDDDtDDoutoutout outDtntdsDI VttVV VVVV VVVtVtVtββ⎧≤⎪⎪=− >−⎨⎪⎛⎞−− < −⎪⎜⎟⎝⎠⎩Vout(t)Vin(t)t0tVin(t)Vout(t)CloadIdsn(t)9/20/2006 VLSI Design I; A. Milenkovic 16Delay Definitions• tpdr:• tpdf:• tpd:• tr:• tf: fall time9/20/2006 VLSI Design I; A. Milenkovic 17Delay Definitions• tpdr: rising propagation delay– From input to rising output crossing VDD/2• tpdf: falling propagation delay– From input to falling output crossing VDD/2• tpd: average propagation delay–tpd= (tpdr+ tpdf)/2• tr: rise time– From output crossing 0.2 VDDto 0.8 VDD• tf: fall time– From output crossing 0.8 VDDto 0.2 VDD9/20/2006 VLSI Design I; A. Milenkovic 18Delay Definitions• tcdr: rising contamination delay– From input to rising output crossing VDD/2• tcdf: falling contamination delay– From input to falling output crossing VDD/2• tcd: average contamination delay–tpd= (tcdr+ tcdf)/29/20/2006 VLSI Design I; A. Milenkovic 19Simulated Inverter Delay• Solving differential equations by hand is too hard• SPICE simulator solves the equations numerically– Uses more accurate I-V models too!• But simulations take time to write (V)0.00.51.01.52.0 t(s)0.0 200p 400p 600p 800p 1ntpdf = 66ps tpdr = 83psVinVout9/20/2006 VLSI Design I; A. Milenkovic 20Delay Estimation• We would like to be able to easily estimate delay– Not as accurate as simulation– But easier to ask “What if?”• The step response usually looks like a 1storder RC response with a decaying exponential.• Use RC delay models to estimate delay– C = total capacitance on output node–Use effective