CPE/EE 427, CPE 527, VLSI Design I: Tutorial #1, Full Custom VLSI (inverter layout) Joel Wilder, Aleksandar Milenkovic, ECE Dept., The University of Alabama in Huntsville Adapted from Virginia Tech, Dept. of Electrical Engineering Authors: Meenatchi Jagasivamani and Jos Sulistyo 1. INTRODUCTION In this tutorial, you will learn how to use Cadence Virtuoso to construct a mask level layout of an inverter. You will manually create the artwork, which specifies transistor layouts and their interconnection. You will then add the I/O pins to the inverter and subsequently verify that there are no design rule errors in the final layout. You will develop a static CMOS inverter onto a p-type silicon substrate; therefore, we will use an NWELL process. Our minimum feature size will be 0.25 microns. It is highly recommended that you read the chapters on CMOS fabrication, layout, and layout design rules in your textbook. 2. CADENCE STARTUP In order to be able to run the Cadence tools, you need to specify a set of environment variables that the tools will need. Do this by editing your .bashrc file in your home directory. At the Unix prompt (indicated by the $ sign) in a terminal window, enter the following: $ xemacs .bashrc Add the following two lines at the end of your .bashrc file: export SKIP_CDS_DIALOG=TRUE uah-cadence-setup The SKIP_CDS_DIALOG variable tells Cadence not to display a startup message when opening the tool. The uah-cadence-setup is a script that contains the necessary environment variables for the tool. You will now need to log out of the unix machine, and then log back in in order for the changes to take affect. After logging back in, in your home directory, create a directory called cadence, where all of your cadence work will be done: $ mkdir cadence Change directories into the cadence folder, create a working folder for lab1_2 (you will use the same folder for tutorials 1 and 2), and change directory: $ cd cadence $ mkdir lab1_2 $ cd lab1_2 Start the cadence tool by entering the following: $ icfb& The command interpreter window (CIW) will appear, as shown in Figure 1.VLSI Design I, Tutorial 1 Page 2 of 13 Figure 1. Command Interpreter Window. 3. CREATE WORK LIBRARY In the CIW, select Tools -> Library Manager, and the Library Manager window will open, as shown in Figure 2. Figure 2. Library Manager.VLSI Design I, Tutorial 1 Page 3 of 13 Next, you will create a library, which will be used to contain the inverter that you will construct. This is done through the Library Manager window by selecting File -> New -> Library. A window will open, as shown in Figure 3. Enter TestLib as the name of the library. Leave the path blank, as this will create a folder in your working directory ($HOME/cadence). Attach a Technology Library by selecting the Attach to existing technology library option and using the associated menu to bring up TSMC 0.24u CMOS025/DEEP (5M, HV FET). This will assign the library you are creating to the TSMC 0.25 µm five-metal, 2.5V process. Press OK and you will notice that your Library Window now contains a library called TestLib. Figure 3. Create Library Window. 4. CREATE INVERTER CELL In the Library Window select TestLib. Then select File -> New -> Cell View and a window will appear as shown in Figure 4. For the Cell Name enter MyINV, and for the Tool, select Virtuoso from the menu.VLSI Design I, Tutorial 1 Page 4 of 13 Figure 4. Create Cell Window. Click OK and two windows will appear. One window is the Layer Selection Window (LSW), which is based on the layers available to the 0.25um process (per the technical library that was attached to the working library, TestLib, that you created), and the other is the Layout Editor window, shown respectively in Figures 5 and 6. Figure 5. Layer Selection Window.VLSI Design I, Tutorial 1 Page 5 of 13 Figure 6. Layout Editor Window. 5. VIRTUOSO SETUP In the Layout Editor window, select Options -> Display, and set the following options in the window: 1. Pin names: On 2. Minor Spacing : 1.08 3. Major Spacing : 4.32 4. X Snap Spacing: 0.06 5. Y Snap Spacing: 0.06 6. Display levels: 7. From: 0 8. To: 30 Select Save To when you are done. Click OK.VLSI Design I, Tutorial 1 Page 6 of 13 MOSIS Design Rules You should follow MOSIS SCN5M_DEEP design rule (http://www.mosis.org/Technical/Layermaps/lm-scmos_scn5m.html) for TSMC 0.25 µm five-metal, 2.5V processing (lambda = 0.12 µm & min. length = 0.24 µm). The inverter consists of three parts -- PMOS, NMOS, and connections. This inverter is routed at the minimum size; therefore, the N- and P-MOSFETS have the same W/L. 6. INVERTER LAYOUT As you go through the layout of the inverter, use Figure 7 as a guideline. Remember to save your design often! Figure 7. Inverter. Layout Editor Useful Information • Shortcut keys can be found in the pulldown windows next to the given commandVLSI Design I, Tutorial 1 Page 7 of 13 • ‘f’ fits the design to the editor window size (zoom in/out using the icons on the side toolbar) • Use the ruler icon for dimensioning. Go to Window->Clear all rulers to delete the ruler markings. • ‘m’ is used to move an object Layout of PMOS with L=0.24 µm and W=0.48 µm. In this tutorial, you are using the NWELL process. Thus, the substrate will be p-substrate. You will create a PMOS transistor first. To do that you will need an NWELL in which the PMOS transistor will be formed. (All work will be done in the Layout Editor window, unless specified for the LSW window.) Draw the well a) Select the n-well layer from the LSW window b) Select the Create->Rectangle (or choose the Rectangle icon from the side toolbar or press the shortcut key ‘r’ on your keyboard). c) Using your mouse, draw the n-well on the cellview to be 2.94 wide by 2.52 tall. NOTE: Use dX and dY at the top of the layout editor window to determine the dimensions. Draw the p-select regions for the PMOS (these regions will contain the diffusion regions) a) Select the pselect layer from the LSW window; we will draw the pselect enclosing the transistor b) Select the Create->Rectangle (or choose the Rectangle icon from the side toolbar or press the shortcut key ‘r’ on your keyboard). c) Using your mouse, draw the pselect on the cellview: 1.98 wide and 0.96 tall; its left- and right-edges should be 0.48 away from well edges. The pselect should be placed within the n-well, even if the size should