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•VLSI Design I; A. Milenkovic •1CPE/EE 427, CPE 527 VLSI Design ISequential CircuitsDepartment of Electrical and Computer Engineering University of Alabama in HuntsvilleAleksandar Milenkovic ( www.ece.uah.edu/~milenka )11/1/2006 VLSI Design I; A. Milenkovic 2Sequencing• Combinational logic– output depends on current inputs• Sequential logic– output depends on current and previous inputs– Requires separating previous, current, future–Called state or tokens– Ex: FSM, pipelineCLclkin outclk clk clkCL CLPipelineFinite State Machine•VLSI Design I; A. Milenkovic •211/1/2006 VLSI Design I; A. Milenkovic 3Sequencing Cont.• If tokens moved through pipeline at constant speed, no sequencing elements would be necessary• Ex: fiber-optic cable– Light pulses (tokens) are sent down cable– Next pulse sent before first reaches end of cable– No need for hardware to separate pulses–But dispersion sets min time between pulses• This is called wave pipelining in circuits• In most circuits, dispersion is high– Delay fast tokens so they don’t catch slow ones.11/1/2006 VLSI Design I; A. Milenkovic 4Sequencing Overhead• Use flip-flops to delay fast tokens so they move through exactly one stage each cycle.• Inevitably adds some delay to the slow tokens• Makes circuit slower than just the logic delay– Called sequencing overhead• Some people call this clocking overhead– But it applies to asynchronous circuits too– Inevitable side effect of maintaining sequence•VLSI Design I; A. Milenkovic •311/1/2006 VLSI Design I; A. Milenkovic 5Sequential LogicCombinationalLogicclockOutputsStateRegistersNextStateCurrentStateInputs11/1/2006 VLSI Design I; A. Milenkovic 6Timing MetricsclockInOutdatastableoutputstableoutputstabletimetimetimeclockDQInOuttsutholdtc-q•VLSI Design I; A. Milenkovic •411/1/2006 VLSI Design I; A. Milenkovic 7System Timing ConstraintsCombinationalLogicclockOutputsStateRegistersNextStateCurrentStateInputsT ≥ tc-q+ tplogic+ tsutcdreg+ tcdlogic≥ tholdT (clock period)11/1/2006 VLSI Design I; A. Milenkovic 8Sequencing Elements• Latch: Level sensitive– a.k.a. transparent latch, D latch• Flip-flop: edge triggered– A.k.a. master-slave flip-flop, D flip-flop, D register• Timing Diagrams– Transparent– Opaque– Edge-triggerDFlopLatchQclk clkDQclkDQ (latch)Q (flop)•VLSI Design I; A. Milenkovic •511/1/2006 VLSI Design I; A. Milenkovic 9Sequencing Elements• Latch: Level sensitive– a.k.a. transparent latch, D latch• Flip-flop: edge triggered– A.k.a. master-slave flip-flop, D flip-flop, D register• Timing Diagrams– Transparent– Opaque– Edge-triggerDFlopLatchQclk clkDQclkDQ (latch)Q (flop)11/1/2006 VLSI Design I; A. Milenkovic 10Latch Design• Pass Transistor Latch• Pros++• Cons––––––DQφ•VLSI Design I; A. Milenkovic •611/1/2006 VLSI Design I; A. Milenkovic 11Latch Design• Pass Transistor Latch• Pros+Tiny+ Low clock load• Cons–Vtdrop– nonrestoring– backdriving– output noise sensitivity– dynamic– diffusion inputDQφUsed in 1970’s11/1/2006 VLSI Design I; A. Milenkovic 12Latch Design• Transmission gate+-DQφφ•VLSI Design I; A. Milenkovic •711/1/2006 VLSI Design I; A. Milenkovic 13Latch Design• Transmission gate+No Vtdrop- Requires inverted clockDQφφ11/1/2006 VLSI Design I; A. Milenkovic 14Latch Design• Inverting buffer+++ Fixes either••–DφφXQDQφφ•VLSI Design I; A. Milenkovic •811/1/2006 VLSI Design I; A. Milenkovic 15Latch Design• Inverting buffer+ Restoring+ No backdriving+ Fixes either• Output noise sensitivity• Or diffusion input– Inverted outputDφφXQDQφφ11/1/2006 VLSI Design I; A. Milenkovic 16Latch Design• Tristate feedback+–φφφφQDX•VLSI Design I; A. Milenkovic •911/1/2006 VLSI Design I; A. Milenkovic 17Latch Design• Tristate feedback+ Static– Backdriving risk• Static latches are now essentialφφφφQDX11/1/2006 VLSI Design I; A. Milenkovic 18Latch Design• Buffered input++φφQDXφφ•VLSI Design I; A. Milenkovic •1011/1/2006 VLSI Design I; A. Milenkovic 19Latch Design• Buffered input+ Fixes diffusion input+ NoninvertingφφQDXφφ11/1/2006 VLSI Design I; A. Milenkovic 20Latch Design• Buffered output+φφQDXφφ•VLSI Design I; A. Milenkovic •1111/1/2006 VLSI Design I; A. Milenkovic 21Latch Design• Buffered output+ No backdriving• Widely used in standard cells+ Very robust (most important)- Rather large- Rather slow (1.5 – 2 FO4 delays)- High clock loadingφφQDXφφ11/1/2006 VLSI Design I; A. Milenkovic 22Latch Design• Datapath latch+-φφφφQDX•VLSI Design I; A. Milenkovic •1211/1/2006 VLSI Design I; A. Milenkovic 23Latch Design• Datapath latch+ Smaller, faster- unbuffered inputφφφφQDX11/1/2006 VLSI Design I; A. Milenkovic 24Flip-Flop Design• Flip-flop is built as pair of back-to-back latchesDQφφφφXDφφφφXQQφφφφ•VLSI Design I; A. Milenkovic •1311/1/2006 VLSI Design I; A. Milenkovic 25Enable• Enable: ignore clock when en = 0– Mux: increase latch D-Q delay– Clock Gating: increase en setup time, skewDQLatchDQenenφφLatchDQφ01enLatchDQφ enDQφ01enDQφ enFlopFlopFlopSymbol Multiplexer Design Clock Gating Design11/1/2006 VLSI Design I; A. Milenkovic 26Reset• Force output low when reset asserted• Synchronous vs. asynchronousDφφφφQQφφφφresetDφφφφφφQφφDresetφφQφφDresetresetφφresetSynchronous Reset Asynchronous ResetSymbolFlopDQLatchDQreset resetφφφφQreset•VLSI Design I; A. Milenkovic •1411/1/2006 VLSI Design I; A. Milenkovic 27Set / Reset• Set forces output high when enabled• Flip-flop with asynchronous set and resetDφφφφφφQφφresetsetresetset11/1/2006 VLSI Design I; A. Milenkovic 28Sequencing Methods• Flip-flops• 2-Phase Latches• Pulsed LatchesFlip-FlopsFlopLatchFlopclkφ1φ2φpclk clkLatchLatchφpφpφ1φ1φ22-Phase Transparent Latches Pulsed LatchesCombinational LogicCombinationalLogicCombinationalLogicCombinational LogicLatchLatchTcTc/2tnonoverlaptnonoverlaptpwHalf-Cycle 1 Half-Cycle 1•VLSI Design I; A. Milenkovic •1511/1/2006 VLSI Design I; A. Milenkovic 29Timing DiagramsFlopAYtpdCombinationalLogicAYDQclkclkDQLatchDQclkclkDQtcdtsetuptholdtccqtpcqtccqtsetuptholdtpcqtpdqtcdqLatch/Flop Hold TimetholdLatch/Flop Setup TimetsetupLatch D-Q Cont. DelaytpcqLatch D-Q Prop DelaytpdqLatch/Flop Clk-Q Cont. DelaytccqLatch/Flop Clk-Q Prop DelaytpcqLogic Cont. DelaytcdLogic Prop.


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