•VLSI Design I; A. Milenkovic •1CPE/EE 427, CPE 527 VLSI Design IWiresDepartment of Electrical and Computer Engineering University of Alabama in HuntsvilleAleksandar Milenkovic ( www.ece.uah.edu/~milenka )10/4/2006 VLSI Design I; A. Milenkovic 2Outline• Introduction• Wire Resistance• Wire Capacitance• Wire RC Delay• Crosstalk• Wire Engineering• Repeaters•VLSI Design I; A. Milenkovic •210/4/2006 VLSI Design I; A. Milenkovic 3Introduction• Chips are mostly made of wires called interconnect– In stick diagram, wires set size– Transistors are little things under the wires– Many layers of wires• Wires are as important as transistors– Speed–Power–Noise• Alternating layers run orthogonally10/4/2006 VLSI Design I; A. Milenkovic 4Wire Geometry• Pitch = w + s• Aspect ratio: AR = t/w– Old processes had AR << 1– Modern processes have AR ≈ 2• Pack in many skinny wireslwsth•VLSI Design I; A. Milenkovic •310/4/2006 VLSI Design I; A. Milenkovic 5Layer Stack• AMI 0.6 µm process has 3 metal layers• Modern processes use 6-10+ metal layers•Example:Intel 180 nm process• M1: thin, narrow (< 3λ)– High density cells• M2-M4: thicker– For longer wires• M5-M6: thickest–For VDD, GND, clkLayer T (nm) W (nm) S (nm) AR6 1720 860 860 2.010005 1600 800 800 2.010004 1080 540 540 2.07003 700 320 320 2. 27002 700 320 320 2. 27001 480 250 250 1. 9800Substrate10/4/2006 VLSI Design I; A. Milenkovic 6Wire Resistanceρ= resistivity (Ω*m)lwtR=•VLSI Design I; A. Milenkovic •410/4/2006 VLSI Design I; A. Milenkovic 7Wire Resistanceρ= resistivity (Ω*m)lwtlRtwρ=10/4/2006 VLSI Design I; A. Milenkovic 8Wire Resistanceρ= resistivity (Ω*m)•R= sheet resistance (Ω/)–  is a dimensionless unit(!)• Count number of squares–R = R* (# of squares)lwt1 Rec tangular Bloc kR = R (L/W) Ω4 Rec tangular BlocksR = R (2L/2W) Ω = R (L/W) Ωtlw wlllRRtw wρ==•VLSI Design I; A. Milenkovic •510/4/2006 VLSI Design I; A. Milenkovic 9Choice of Metals• Until 180 nm generation, most wires were aluminum• Modern processes often use copper– Cu atoms diffuse into silicon and damage FETs– Must be surrounded by a diffusion barrier5.3Molybdenum (Mo)5.3Tungsten (W)2.8Aluminum (Al)2.2Gold (Au)1.7Copper (Cu)1.6Silver (Ag)Bulk resistivity (µΩ*cm)Metal10/4/2006 VLSI Design I; A. Milenkovic 10Sheet Resistance• Typical sheet resistances in 180 nm process0.08Metal10.05Metal20.05Metal30.03Metal40.02Metal60.02Metal550-400Polysilicon (no silicide)3-10Polysilicon (silicided)50-200Diffusion (no silicide)3-10Diffusion (silicided)Sheet Resistance (Ω/)Layer•VLSI Design I; A. Milenkovic •610/4/2006 VLSI Design I; A. Milenkovic 11Contacts Resistance• Contacts and vias also have 2-20 Ω• Use many contacts for lower R– Many small contacts for current crowding around periphery10/4/2006 VLSI Design I; A. Milenkovic 12Wire Capacitance• Wire has capacitance per unit length– To neighbors– To layers above and below•Ctotal= Ctop+ Cbot+ 2Cadjlayer n+1layer nlayer n-1CadjCtopCbotwsth1h2•VLSI Design I; A. Milenkovic •710/4/2006 VLSI Design I; A. Milenkovic 13Capacitance Trends• Parallel plate equation: C = εA/d– Wires are not parallel plates, but obey trends– Increasing area (W, t) increases capacitance– Increasing distance (s, h) decreases capacitance• Dielectric constant– ε = kε0• ε0= 8.85 x 10-14F/cm• k = 3.9 for SiO2• Processes are starting to use low-k dielectrics–k ≈ 3 (or less) as dielectrics use air pockets10/4/2006 VLSI Design I; A. Milenkovic 14M2 Capacitance Data• Typical wires have ~ 0.2 fF/µm– Compare to 2 fF/µm for gate capacitance0501001502002503003504000 500 1000 1500 2000Ctotal (aF/µm)w (nm)IsolatedM1, M3 planess = 320s = 480s = 640s=8s = 320s = 480s = 640s=8•VLSI Design I; A. Milenkovic •810/4/2006 VLSI Design I; A. Milenkovic 15Diffusion & Polysilicon• Diffusion capacitance is very high (about 2 fF/µm)– Comparable to gate capacitance– Diffusion also has high resistance– Avoid using diffusion runners for wires!• Polysilicon has lower C but high R– Use for transistor gates– Occasionally for very short wires between gates10/4/2006 VLSI Design I; A. Milenkovic 16Lumped Element Models• Wires are a distributed system– Approximate with lumped element models• 3-segment π-model is accurate to 3% in simulation• L-model needs 100 segments for same accuracy!• Use single segment π-model for Elmore delayCRC/NR/NC/NR/NC/NR/NC/NR/NRCL-modelRC/2 C/2R/2 R/2CN segmentsπ-model T-model•VLSI Design I; A. Milenkovic •910/4/2006 VLSI Design I; A. Milenkovic 17Example• Metal2 wire in 180 nm process– 5 mm long– 0.32 µm wide• Construct a 3-segment π-model–R=–Cpermicron=10/4/2006 VLSI Design I; A. Milenkovic 18Example• Metal2 wire in 180 nm process– 5 mm long– 0.32 µm wide• Construct a 3-segment π-model–R= 0.05 Ω/ => R = 781 Ω–Cpermicron= 0.2 fF/µm => C = 1 pF260 Ω167 fF167 fF260 Ω167 fF167 fF260 Ω167 fF167 fF•VLSI Design I; A. Milenkovic •1010/4/2006 VLSI Design I; A. Milenkovic 19Wire RC Delay• Estimate the delay of a 10x inverter driving a 2x inverter at the end of the 5mm wire from the previous example.–R = 2.5 kΩ*µm for gates– Unit inverter: 0.36 µm nMOS, 0.72 µm pMOS–tpd=10/4/2006 VLSI Design I; A. Milenkovic 20Wire RC Delay• Estimate the delay of a 10x inverter driving a 2x inverter at the end of the 5mm wire from the previous example.–R = 2.5 kΩ*µm for gates– Unit inverter: 0.36 µm nMOS, 0.72 µm pMOS–tpd= 1.1 ns781 Ω500 fF500 fFDriver Wire4 fFLoad690 Ω•VLSI Design I; A. Milenkovic •1110/4/2006 VLSI Design I; A. Milenkovic 21Crosstalk• A capacitor does not like to change its voltage instantaneously.• A wire has high capacitance to its neighbor.– When the neighbor switches from 1-> 0 or 0->1, the wire tends to switch too.– Called capacitive coupling or crosstalk.• Crosstalk effects– Noise on nonswitching wires– Increased delay on switching wires10/4/2006 VLSI Design I; A. Milenkovic 22Crosstalk Delay• Assume layers above and below on average are quiet– Second terminal of capacitor can be ignored– Model as Cgnd = Ctop + Cbot• Effective Cadj depends on behavior of neighbors– Miller effectA BCadjCgndCgndSwitching opposite ASwitching with AConstantMCFCeff(A)∆VB•VLSI Design I; A. Milenkovic •1210/4/2006 VLSI Design I;