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UAH CPE 427 - CMOS Inverter

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•VLSI Design I; A. Milenkovic •1CPE/EE 427, CPE 527 VLSI Design IL05: CMOS InverterDepartment of Electrical and Computer Engineering University of Alabama in HuntsvilleAleksandar Milenkovic ( www.ece.uah.edu/~milenka )www.ece.uah.edu/~milenka/cpe527-05F9/10/2005 VLSI Design I; A. Milenkovic 2Course Administration• Instructor: Aleksandar [email protected]/~milenkaEB 217-LMon. 5:30 PM – 6:30 PM, Wen. 12:30 – 13:30 PM •URL: http://www.ece.uah.edu/~milenka/cpe527-05F• TA: Joel Wilder• Labs: Lab#2 posted (due 9/23/05)• Text: CMOS VLSI Design, 3rded., Weste, Harris• Review: Introduction, Design Metrics, IC Fabrication (Read Chapter 1); IC Fabrication (Chapter 3)• Today: MOS Non-ideal IV, CMOS Inverter (Chapter 2)•VLSI Design I; A. Milenkovic •29/10/2005 VLSI Design I; A. Milenkovic 3Non-Ideal I-V Effects•Ids(sat) increasesless than quadratically with increasing Vgs– Velocity saturation & mobility degradation•Ids(sat) increasesslightly with Vds– Channel length modulation•VTis influenced by the Vsb– Body effect• There is current flow in nominally OFF transistors– Subthreshold conduction (junction leakage, tunnel)()2cutofflinearsaturatio022ngs tdsds gs t ds ds dsatgs t ds dsatVVVIVVVVVVV VVββ⎧⎪<⎪⎪⎛⎞=−− <⎜⎟⎨⎝⎠⎪⎪−>⎪⎩9/10/2005 VLSI Design I; A. Milenkovic 4Current Determinates• For a fixed VDSand VGS(> VT), IDSis a function of– the distance between the source and drain – L– the channel width – W– the threshold voltage – VT– the thickness of the SiO2–tox– the dielectric of the gate insulator (SiO2) – εox– the carrier mobility• for nfets: µn= 500 cm2/V-sec• for pfets: µp= 180 cm2/V-sec•VLSI Design I; A. Milenkovic •39/10/2005 VLSI Design I; A. Milenkovic 5Long Channel I-V Plot (NMOS)01234560 0.5 1 1.5 2 2.5ID(A)VDS(V)X 10-4VGS= 1.0VVGS= 1.5VVGS= 2.0VVGS= 2.5VLinear SaturationVDS= VGS-VTQuadraticdependenceNMOS transistor, 0.25um, Ld= 10um, W/L = 1.5, VDD= 2.5V, VT= 0.4Vcut-off9/10/2005 VLSI Design I; A. Milenkovic 6Short Channel Effectsυsat=105z For an NMOS device with L of .25µm, only a couple of volts difference between D and S are needed to reach velocity saturationz Behavior of short channel device mainly due to• Velocity saturation –the velocity of the carriers saturates due to scattering (collisions suffered by the carriers)01001.53ξ(V/µm)υn(m/s)Constant velocityConstant mobility(slope = µ)ξc=5•VLSI Design I; A. Milenkovic •49/10/2005 VLSI Design I; A. Milenkovic 7Voltage-Current Relation: Velocity SaturationFor short channel devices• Linear: When VDS≤ VGS–VTID= κ(VDS) k’nW/L [(VGS–VT)VDS–VDS2/2]whereκ(V) = 1/(1 + (V/ξcL)) is a measure of the degree of velocity saturation• Saturation: When VDS= VDSAT≥ VGS–VTIDSat= κ(VDSAT) k’nW/L [(VGS–VT)VDSAT–VDSAT2/2]9/10/2005 VLSI Design I; A. Milenkovic 8Velocity Saturation Effects010Long channel devicesShort channel devicesVDSATVGS-VT•VDSAT< VGS–VT so the device enters saturation before VDSreaches VGS–VT and operates more often in saturationFor short channel devices and large enough VGS–VT•IDSAThas a linear dependence wrt VGS so a reduced amount of current is delivered for a given control voltageVGS= VDD•VLSI Design I; A. Milenkovic •59/10/2005 VLSI Design I; A. Milenkovic 9Short Channel I-V Plot (NMOS)00.511.522.50 0.5 1 1.5 2 2.5ID(A)VDS(V)X 10-4VGS= 1.0VVGS= 1.5VVGS= 2.0VVGS= 2.5VLineardependenceNMOS transistor, 0.25um, Ld= 0.25um, W/L = 1.5, VDD= 2.5V, VT= 0.4VEarly VelocitySaturationLinear Saturation9/10/2005 VLSI Design I; A. Milenkovic 10MOS ID-VGSCharacteristics01234560 0.5 1 1.5 2 2.5VGS(V)ID(A)longlong--channel channel quadraticquadraticshort-channel linear• Linear (short-channel) versus quadratic (long-channel) dependence of IDon VGSin saturation• Velocity-saturation causes the short-channel device to saturate at substantially smaller values of VDSresulting in a substantial drop in current drive(for VDS = 2.5V, W/L = 1.5)X 10-4•VLSI Design I; A. Milenkovic •69/10/2005 VLSI Design I; A. Milenkovic 11Short Channel I-V Plot (PMOS)-1-0.8-0.6-0.4-0.200-1-2ID(A)VDS(V)X 10-4VGS= -1.0VVGS= -1.5VVGS= -2.0VVGS= -2.5VPMOS transistor, 0.25um, Ld= 0.25um, W/L = 1.5, VDD= 2.5V, VT= -0.4V• All polarities of all voltages and currents are reversed9/10/2005 VLSI Design I; A. Milenkovic 12Transistor in Saturation ModeSDBGVGSVDS > VGS-VTIDVGS-VT-+n+ n+Pinch-offAssuming VGS > VTVDSThe current remains constant (saturates).•VLSI Design I; A. Milenkovic •79/10/2005 VLSI Design I; A. Milenkovic 13Voltage-Current Relation: Saturation ModeFor long channel devices• When VDS≥ VGS–VTID’ = k’n/2 W/L [(VGS–VT) 2]since the voltage difference over the induced channel (from the pinch-off point to the source) remains fixed at VGS–VT• However, the effective length of the conductive channel is modulated by the applied VDS, soID= ID’ (1 + λVDS)where λ is the channel-length modulation(varies with the inverse of the channel length)9/10/2005 VLSI Design I; A. Milenkovic 14Threshold Voltage ConceptSDp substrateBGVGS +-n+n+depletion regionn channelThe value of VGSwhere strong inversion occurs is called the threshold voltage, VT•VLSI Design I; A. Milenkovic •89/10/2005 VLSI Design I; A. Milenkovic 15The Threshold VoltageVT= VT0+ γ(√|-2φF+ VSB| - √|-2φF|)whereVT0 is the threshold voltage at VSB= 0 and is mostly a function of the manufacturing process– Difference in work-function between gate and substrate material, oxide thickness, Fermi voltage, charge of impurities trapped at the surface, dosage of implanted ions, etc.VSBis the source-bulk voltageφF= -φTln(NA/ni) is the Fermi potential (φT= kT/q = 26mV at 300K is the thermal voltage; NAis the acceptor ion concentration; ni≈ 1.5x1010cm-3at 300K is the intrinsic carrier concentration in pure silicon)γ = √(2qεsiNA)/Coxis the body-effect coefficient (impact of changes in VSB) (εsi=1.053x10-10F/m is the permittivity of silicon; Cox= εox/toxis the gate oxide capacitance with εox=3.5x10-11F/m)9/10/2005 VLSI Design I; A. Milenkovic 16The Body Effect0.40.450.50.550.60.650.70.750.80.850.9-2.5 -2 -1.5 -1 -0.5 0•VSBis the substrate bias voltage (normally positive for n-channel devices with the body tied to ground)• A negative bias causes VTto increase from 0.45V to 0.85VVBS(V)VT(V)•VLSI Design I; A. Milenkovic •99/10/2005 VLSI Design I; A. Milenkovic 17Other


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