VHDL OverviewReading for this LectureOutlineWhat is VHDL?A NAND Gate ExampleAnother Implementation of NANDYet More NAND Gates!The process StatementThe wait StatementA Simple Producer-Consumer ExampleProducer-Consumer in VHDLProducer-Consumer in VHDL 4-Phase CaseMuller C ElementA Edge Triggered D Flip-FlopA Edge Triggered D Flip-Flop (contd.)Behavior vs. Structure DescriptionXOR in VHDL: BehaviorXOR in VHDL: StructureXOR in VHDL: MixedThe Generate StatementThe Generate Statement (contd.)Concurrent vs. Sequential StatementsSlide 23VHDL’s Model of a SystemSimilar to an OSAnatomy of the VHDL KernelSignals versus VariablesTransaction Delay ModelsCase 1: Transport Delay ModelTransport Delay Model (contd.)Case 2: Inertial Delay ModelInertial Delay Model (contd.)Slide 33Signals with Multiple DriversResolution Function Example: Wire-And (open collector)Guarded Signals: register & busGuarded Signals (contd.)Using VHDL Like C!Language Features: TypesExamples of VHDL TypesLanguage Features: SubtypesArray and Record TypesLanguage Features: OverloadingOverloading (contd.)Language Features: ConfigurationsConfigurations (contd.)Language Features: PackagesExample of a PackageLanguage Features: Design Units and LibrariesDesign Units and Libraries (contd.)Logic Simulation in VHDLA Typical VHDL Simulator (MCC)Mani SrivastavaUCLA - EE [email protected] OverviewEE116B (Winter 2001): Lecture # 5Copyright 2001  Mani Srivastava2Reading for this LectureAshenden’s bookChapters 1-5, Appendix A, E, FAlso recommended Chapters 6, 12, 13, 15Copyright 2001  Mani Srivastava3OutlineIntroduction to the languagesimple examplesVHDL’s model of a systemits computation model: processes, signals and timeLanguage featuresVHDL use in logic simulationCopyright 2001  Mani Srivastava4What is VHDL?Programming Language + Hardware Modeling LanguageIt has all of the following:Sequential Procedural language: PASCAL and ADA likeConcurrency: statically allocated network of processesTiming constructsDiscrete-event simulation semanticsObject-oriented goodies: libraries, packages, polymorphismCopyright 2001  Mani Srivastava5A NAND Gate Example-- black-box definition (interface)entity NAND isgeneric ( Tpd : time := 0 ns );port ( A, B : in bit; Y : out bit );end NAND;-- an implementation (contents)architecture BEHAVIOR_1 of NAND isbeginY <= A nand B after Tpd;end BEHAVIOR_1;ABYImportant Conceptsentityarchitecturegene ricportwaveform assignmentCopyright 2001  Mani Srivastava6Another Implementation of NAND-- there can be multiple implementationsarchitecture BEHAVIOR_2 of NAND issignal X : bit;begin-- concurrent statementsY <= X after Tpd;X <= ‘1’ when A=’0’ or B=’0’ else ‘0’;end BEHAVIOR_2;ABYImportant Conceptsmultiple architecturessignalconcurrent statementsCopyright 2001  Mani Srivastava7Yet More NAND Gates!entity NAND_N isgeneric ( N : integer := 4; Tpd : time);port ( A, B : in bit_vector(1 to N);Y : out bit_vector(1 to N));end NAND_N;architecture BEHAVIOR_1 of NAND_N isbeginprocessvariable X : bit_vector(1 to N);beginX := A nand B;Y <= X after Td;wait on A, B;end process;end BEHAVIOR_1;Important Conceptsprocessvariablewaitsequential statementseventsCopyright 2001  Mani Srivastava8The process Statement[label:] process [(sensitivity_list)] [declarations]begin {sequential_statement}end process [label];It defines an independent sequential process which repeatedly executes its bodyFollowing are equivalent:process (A,B) processbegin begin C <= A or B; C <= A or B;end; wait on A, B;end;No wait statements allowed in the body if there is a sensitivity_listCopyright 2001  Mani Srivastava9The wait Statementwait [on list_of_signals] [until boolean_expression] [for time_expression] ;This is the ONLY sequential statement during which time advances!examples:-- wait for a rising or falling edge on CLKwait on CLK;wait until CLK’EVENT; -- this is equivalent to the above-- wait for rising edge of CLKwait on CLK until CLK=’1’;wait until CLK=’1’; -- this is equivalent to the above-- wait for 10 nswait until 10 ns;-- wait for ever (the process effectively dies!)wait;Copyright 2001  Mani Srivastava10A Simple Producer-Consumer ExampleProduces ConsumerDATAREQACKCopyright 2001  Mani Srivastava11Producer-Consumer in VHDLentity producer_consumer isend producer_comsumer;architecture two_phase of producer_consumer issignal REQ, ACK : bit;signal DATA : integer;beginP: process beginDATA <= produce();REQ <= not REQ;wait on ACK;end P;C: process beginwait on REQ;consume(DATA);ACK <= not ACK;end C; end two_phase;Copyright 2001  Mani Srivastava12Producer-Consumer in VHDL4-Phase Casearchitecture four_phase of producer_consumer issignal REQ, ACK : bit := ‘0’;signal DATA : integer;beginP: process beginDATA <= produce();REQ <= ‘1’;wait until ACK=’1’;REQ <= ‘0’;wait until ACK=’0’;end P;C: process beginwait until REQ=’1’;consume(DATA);ACK <= ‘1’;wait until REQ=’0’;ACK <= ‘0’;end C; end four_phase;Copyright 2001  Mani Srivastava13Muller C Elemententity MULLER_C_ELEMENT isport (A,B : in bit; C : out bit);end MULLER_C_ELEMENT;architecture BEHAVIOR isbeginprocess begin wait until A=’1’ and B=’1’; C <= ‘1’; wait until A=’0’ and B=’0’; C <= ‘0’;end process;end BEHAVIOR;Could have written:wait until A=B;C <= A;CABCCopyright 2001  Mani Srivastava14A Edge Triggered D Flip-Flopentity DFF isgeneric (T_setup, T_hold, T_delay : time:=0 ns);port (D, CLK: in bit; Q : out bit);begin-- check setup timeassert not (CLK’EVENT and CLK=’1’ and D’LAST_EVENT < T_setup)report “Setup violation”severity WARNING;-- check hold timeassert not (CLK’DELAYED(T_hold)’EVENT and CLK’DELAYED(Thold)=’1’ and D’LAST_EVENT < T_hold)report “Hold violation”severity WARNING;end DFF;Copyright 2001  Mani Srivastava15A Edge Triggered D Flip-Flop (contd.)architecture BEHAVIOR of DFF isbeginprocess beginwait on CLK until CLK=’1’;Q <= D after T_delay;end process;end BEHAVIOR;Copyright 2001  Mani Srivastava16Behavior vs. Structure DescriptionAn entity can be described by its behavior or by its structure, or in a mixed fashionExample: a 2-input XOR gateABYY = A.B+A.BABYG1G2G4G3Copyright 2001  Mani Srivastava17XOR in VHDL: Behaviorentity XOR isport ( A,B : in bit; Y : out bit);end XOR;architecture BEHAVIOR of XOR isbeginY <= (A and not B) or (not A