A Really Rapid Review of CMOS CircuitsReading for this LecturePhysical Structure of MOS FETS2-D Representation of MOS TransistorThreshold Voltage ConceptCurrent-Voltage RelationsTransistor in SaturationSwitch-Level View of NMOS & PMOSThe CMOS TechnologyCMOS SwitchCMOS InverterCMOS Inverter LayoutNMOS Switches in SeriesPMOS Switches in SeriesSwitches in Parallel2-Input CMOS NAND Gate: the Switch View2-Input CMOS NAND Gate: the Circuit ViewN-input CMOS NAND Gate4-Input NAND Gate2-Input CMOS OR-GateN-Input CMOS OR-GateProperties of CMOS GatesMaking Compound Gates in CMOSKey Idea in CMOS Compound Logic GatesMore on CMOS Logic StylePull-Up and Pull-Down CircuitsCMOS Compound GateWhat is this?How do we implement these?A 2-Input CMOS MultiplexerHow can one implement multiplexer using CMOS gates?Layout: the Standard Cell ApproachTwo versions of a.(b+c)Logic GraphConsistent Euler PathExample: x = ab + cdExistence of Consistent Euler PathsMemory & Storage in CMOSA CMOS Positive Level-Sensitive D LatchA CMOS Positive Edge-Triggered D RegisterPerformance Analysis of CMOS GatesMOS Transistors are not “Ideal” SwitchesCMOS Inverter: A More Detailed ViewCMOS Inverter: Steady State ResponseCMOS Inverter: Transient ResponseWhat is the value of Ron?Numerical Examples for 1.2m CMOSTransistor SizingPropagation Delay AnalysisAnalysis of Propagation DelayDesign for Worst CaseInfluence of Fan-in and Fan-out on Delaytp as a Function of Fan-inFast Complex Gates - IFast Complex gates - IIFast Complex Gates - IIIFast Complex Gates - IVExample: Full AdderRevised Full AdderMani SrivastavaUCLA - EE DepartmentRoom: 7702-B Boelter HallEmail: [email protected]: 310-267-2098WWW: http://www.ee.ucla.edu/~mbsCopyright 2002  Mani Srivastava A Really Rapid Reviewof CMOS CircuitsEE116B (Winter 2002): Lecture #22Copyright 2002  Mani SrivastavaReading for this LectureReview EE115C notesRabaey CH 3, 4, and 63Copyright 2002  Mani SrivastavaPhysical Structure of MOS FETS[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]NMOSPMOS4Copyright 2002  Mani Srivastava2-D Representation of MOS Transistor[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]5Copyright 2002  Mani SrivastavaThreshold Voltage Conceptn+n+p-substrateDSGBVGS+-DepletionRegionn-channel[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]6Copyright 2002  Mani SrivastavaCurrent-Voltage Relations[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]7Copyright 2002  Mani SrivastavaTransistor in Saturationn+n+SGVGSDVDS > VGS - VTVGS - VT+-[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]8Copyright 2002  Mani SrivastavaSwitch-Level View of NMOS & PMOS[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]9Copyright 2002  Mani SrivastavaThe CMOS Technology[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]10Copyright 2002  Mani SrivastavaCMOS Switch[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]11Copyright 2002  Mani SrivastavaCMOS Inverter[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]12Copyright 2002  Mani SrivastavaCMOS Inverter LayoutPolysiliconInOutMetal1VDDGNDPMOSNMOS1.2 m=2[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]13Copyright 2002  Mani SrivastavaNMOS Switches in Series[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]14Copyright 2002  Mani SrivastavaPMOS Switches in Series[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]15Copyright 2002  Mani SrivastavaSwitches in Parallel[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]16Copyright 2002  Mani Srivastava2-Input CMOS NAND Gate: theSwitch View[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]17Copyright 2002  Mani Srivastava2-Input CMOS NAND Gate: theCircuit View[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]18Copyright 2002  Mani SrivastavaN-input CMOS NAND Gate[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]19Copyright 2002  Mani Srivastava4-Input NAND GateOutIn1 In2 In3 In4In3In1In2In4In1In2In3In4VDDOutGNDVDDIn1 In2 In3 In4VddGNDOut[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]20Copyright 2002  Mani Srivastava2-Input CMOS OR-Gate[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]21Copyright 2002  Mani SrivastavaN-Input CMOS OR-Gate[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]22Copyright 2002  Mani SrivastavaProperties of CMOS GatesVdd and GND are never directly connectedi.e. no shortingOutput is always connected to either Vdd or GNDi.e. it never floats23Copyright 2002  Mani SrivastavaMaking Compound Gates in CMOSF = ((A.B) + (C.D))[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]24Copyright 2002  Mani SrivastavaKey Idea in CMOS Compound Logic GatesVDDVSSPUNPDNIn1In2In3F = GIn1In2In3PUN and PDN are Dual NetworksPMOS OnlyNMOS Only[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]25Copyright 2002  Mani SrivastavaMore on CMOS Logic Style[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]26Copyright 2002  Mani SrivastavaPull-Up and Pull-Down Circuits[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]27Copyright 2002  Mani SrivastavaCMOS Compound Gate[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]28Copyright 2002  Mani SrivastavaWhat is this?[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]29Copyright 2002  Mani SrivastavaHow do we implement these?Z = (A.B.C.D)’Z = ((A.B) + C.(A+B))’Z = A.B + A’.B’what is this?Z = A.B’.C’ + A’.B’.C + A’.C’.B + A.B.Cwhat is this?30Copyright 2002  Mani SrivastavaA 2-Input CMOS MultiplexerOutput = A.S + B.S’[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]31Copyright 2002  Mani SrivastavaHow can one implement multiplexer using CMOS gates?32Copyright 2002  Mani SrivastavaLayout: the Standard Cell ApproachVDDVSSWellsignalsRouting Channelmetal1polysilicon[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]33Copyright 2002  Mani SrivastavaTwo versions of a.(b+c)a c b a b cxxGNDVDDVDDGND(a) Input order {a c b}(b) Input order {a b c}[Adapted