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UCLA EE 116B - L8

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Architecture Issues in VLSI SystemsArchitecture Techniques in VLSIPipelining and RetimingRetimingHow does Retiming help?Clock Period MinimizationClock Period Minimization (contd.)Slide 8Retiming for Register MinimizationExample of Retiming for Register MinimizationLoop BoundSlide 12Iteration Bound TIteration Bound T (contd.)Another Trick: UnfoldingUnfolding (contd.)How to do Unfolding?Another ExampleHow does Unfolding help?Example of Case 1Example of Case 2Power Consumption in CMOS Digital LogicPower Consumption in CMOS Digital logic (contd.)Why not simply lower V?Speed vs. VoltageReducing the Supply Voltage: an Architectural ApproachExample: Voltage-Parallelism Trade-offSlide 28Slide 29Pipelined DatapathDatapath Architecture-Power Trade-off SummaryExample of Voltage ScalingApproaches to Energy EfficiencyShutdown for Energy SavingPotential CPU Power Reduction in a Wireless X TerminalProblems in ShutdownTo Shutdown or Reduce Voltage?Shutdown vs. Voltage ReductionProblem with Voltage ReductionDynamically Variable VoltageVarying the Supply VoltageWorkload Averaging HelpsAdaptive Voltage ScalingAdaptive Voltage Scaling in Synchronous SystemsMani SrivastavaUCLA - EE DepartmentRoom: 7702-B Boelter HallEmail: [email protected]: 310-267-2098WWW: http://www.ee.ucla.edu/~mbsCopyright 2002  Mani SrivastavaArchitecture Issues in VLSI Systems EE116B (Winter 2002): Lecture # 8Copyright 2002  Mani SrivastavaArchitecture Techniques in VLSIBig impact of architectural level techniques and optimizationsPerformancePowerCopyright 2002  Mani SrivastavaPipelining and Retiming+D DD+DDGDDG’D DDDPipeliningRetimingD (a) * D (b) = D (a * b)D = RegisterCopyright 2002  Mani SrivastavaRetimingCopyright 2002  Mani SrivastavaHow does Retiming help?++++DD87561234++++DD87561234DDCYCLES Multipliers Adders1 1,3 -2 2,4 53 - 6,84 - 7CYCLES Multipliers Adders1 2 82 3 63 1 74 4 5before afterCopyright 2002  Mani SrivastavaClock Period MinimizationExample: 100 stage lattice filterAssume add and multiply take 1 and 2 units of time respectivelyCritical path in dotted lineMinimum sample period = 105Copyright 2002  Mani SrivastavaClock Period Minimization (contd.)2-slowdown versionCopyright 2002  Mani SrivastavaClock Period Minimization (contd.)Retimed version of the 2-slow down modelCritical path = 6Minimum sample period = 12Copyright 2002  Mani SrivastavaRetiming for Register MinimizationCopyright 2002  Mani SrivastavaExample of Retiming for Register MinimizationCopyright 2002  Mani SrivastavaLoop Boundy(n) = a.y(n-1) + x(n)Critical path: longest path with zero delaysA->B has length 6Intra-iteration precedence vs. Inter-iteration precedenceAB and BACopyright 2002  Mani SrivastavaLoop BoundTwo critical paths of length 663215 321But what is the fundamental limit on how fast can the underlying circuit be implemented?Copyright 2002  Mani SrivastavaIteration Bound TIteration boundExample: three loops with loop bounds of4/2, 5/3, 5/4T = 2Copyright 2002  Mani SrivastavaIteration Bound T (contd.)T = 3T = max(6/2, 11/1) = 11Copyright 2002  Mani SrivastavaAnother Trick: UnfoldingCopyright 2002  Mani SrivastavaUnfolding (contd.)Copyright 2002  Mani SrivastavaHow to do Unfolding?Copyright 2002  Mani SrivastavaAnother ExampleCopyright 2002  Mani SrivastavaHow does Unfolding help?Unfolding a circuit with iteration bound T results in a J-unfolded circuit with iteration bound JTSeems like no win, but can help with actual sample period in two scenariosCase 1: sample period could not be made equal to iteration period because of some node with computation time greater than TCase 2: sample period could not be made equal to iteration period because T is not an integerCopyright 2002  Mani SrivastavaExample of Case 1T=3Minimum sample period = 4T=6Minimum sample period = 6/2=3Copyright 2002  Mani SrivastavaExample of Case 2T=4/3Minimum sample period = 2T=4Minimum sample period = 4/3Copyright 2002  Mani SrivastavaPower Consumption in CMOS Digital LogicDynamic power consumptioncharging and discharging capacitorsShort circuit currentsshort circuit path between supply rails during switchingLeakageleaking diodes and transistorsproblem even when in standby!Copyright 2002  Mani SrivastavaPower Consumption in CMOS Digital logic (contd.)P = A.C.V2.f + A.Isw.V.f + Ileak.VwhereA = activity factor (probability of 0  1 transition)C = total chip capacitanceV = total voltage swing, usually near the power supply voltagef = clock frequencyIsw = short circuit current when logic level changesIleak = leakage current in diodes and transistorsCopyright 2002  Mani SrivastavaWhy not simply lower V?Total P can be minimized by lower Vlower V are a natural result of smaller feature sizesBut… transistor speeds decrease dramatically as V is reduced to close to “threshold voltage”performance goals may not be mettd = CV / k(V-Vt) where  is between 1-2 Why not lower this “threshold voltage”?makes noise margin and Ileak worse!Need to do smarter voltage scaling!Copyright 2002  Mani SrivastavaSpeed vs. Voltage1.0 1.5 2.0 2.5 3.0Supply Voltage, V1.03.05.07.0Normalized DelayCopyright 2002  Mani SrivastavaReducing the Supply Voltage: an Architectural ApproachOperate at reduced voltage at lower speedUse architecture optimization to compensate for slower operatione.g. concurrency, pipelining via compiler techniquesArchitecture bottlenecks limit voltage reductiondegradation of speed-upinterconnect overheadsSimilar idea for memory: slower and parallelTrade-off AREA for lower POWERCopyright 2002  Mani SrivastavaExample: Voltage-Parallelism Trade-off1.0 1.5 2.0 2.5 3.0Supply Voltage, V1.03.05.07.0Normalized Delay1 2 3 4 5 6 7 8Parallelism, N1.03.05.07.0Ideal SpeedupSpeedupCopyright 2002  Mani SrivastavaExample: Reference Datapathfrom “Digital Integrated Circuits” by Rabaey Critical path delay: Tadder + Tcomparator = 25 ns Frequency: fref = 40 MHz Total switched capacitance = Cref Vdd = Vref = 5V Power for reference datapath = Pref = CrefVref2frefCopyright 2002  Mani SrivastavaParallel Datapathfrom “Digital Integrated Circuits” by Rabaey The clock rate can be reduced by x2 with the same throughput: fpar = fref/2 = 20 MHz


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UCLA EE 116B - L8

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