VLSI Systems DesignCourse GoalsYou will NOT learn...ScheduleMore on Lab SessionsCourse StaffPrerequisites & GradingCheating & PlagiarismBooksLecture NotesComputer AccountsCourse on the InternetGroups for Design AssignmentsConflict with Conference TravelExamsFinal WordsQuestions?Issues & Trends in VLSI DesignMoore’s LawEvolution in Transistor Count: Logic ICsEvolution in Transistor Count: Memory ICsEvolution in Transistor Count: MicroprocessorsEvolution in ComplexityEvolution in Speed & PerformanceRecent ChipsSematech’s International Technology Roadmap for Semiconductors (ITRS) (http://public.itrs.net/)The Design ProblemProfound Impact on the way VLSI is DesignedDesign Abstraction LevelsThe Transistor Twiddling & Rectangle Pushing ApproachDesign with CAD ToolsCan’t Ignore “Transistor Twiddling”The Old and the NewPentium IIICore-based Design: System on ChipTopics Covered in this CourseTopics Covered in this Course (contd.)Mani SrivastavaUCLA - EE DepartmentRoom: 7702-B Boelter HallEmail: [email protected]: 310-267-2098WWW: http://www.ee.ucla.edu/~mbsCopyright 2002 Mani SrivastavaVLSI Systems DesignEE116B (Winter 2002): Lecture #12Copyright 2002 Mani SrivastavaCourse GoalsMain objectiveoverview of various steps in digital CMOS VLSI design–circuit, logic, and architecture issues–design tools and techniques–engineering issues for performance, noise, testability etc.Approachlectures to present VLSI design conceptsregular homework will test you on the conceptsdesign assignments will expose you to CAD tool based VLSI design3Copyright 2002 Mani SrivastavaYou will NOT learn...Device physicsSemiconductor processingFancy circuitsAdvanced logicComputer architectureWriting CAD toolsAnalog VLSIVLSI using technologies other than CMOS (e.g. bipolar, GaAs etc.)4Copyright 2002 Mani SrivastavaScheduleLecturesTuTh 10-11:50AM @ Boelter 5422Discussion (supervised by TA)Fr 12-12:50PM @ Boelter 5280Laboratory (supervised by TA)We 12-3:50PM @ EIV 44-1105Copyright 2002 Mani SrivastavaMore on Lab SessionsThere will usually not be any formal “lecturing” in the labsThe purpose is to have a period of time whenyou’ve guaranteed access to computers for design assignments•SEASnet labs are very crowdedTA is present to supervise & help you with the design assignmentI can come and see everybody’s progress and explain things•Usually, I will come for an hour at the beginning of every labHowever, the four hour lab sessions are not at all enough…be prepared for spending a LOT of time on design assignments outside the regular lab sessions (44-110 EIV is closed/busy)Coming to lab sessions is strongly encouragedotherwise you will miss important assignment related announcements and fall behind very easilyUltimately, you are responsible for timely submission6Copyright 2002 Mani SrivastavaCourse StaffInstructor: Mani SrivastavaEmail: [email protected]Tel: 310-267-2098Office: 7702-B Boelter Hall (will change to 6731H Boelter soon)Office Hours: We 11-12, Th 12:30-1:30Teaching Assistant: Shalabh GuptaEmail: [email protected]Office Hours: Mo 12-1, Fr 1-2 in EIV 44-110Administrative Assistant: Leticia Marr (Letty)Email: [email protected]Tel: 310-267-1954Office: 7440-D Boelter HallHours: M-F 8-57Copyright 2002 Mani SrivastavaPrerequisites & GradingPrerequisitesunderstanding of circuits and digital logic & systems–EE115C, EE16, some advanced digital design course (any of EE116L, EE116C, EE116D etc.)GradingMidterm, surprise quizzes: 20%Final: 30%Homework assignments (2-3): 15%Design lab assignments (2-4): 35%Regular attendance is mandatory. Unsatisfactory attendance andparticipation in the class (lecture, lab, discussion section) will reduceyour final score by up to 20%.8Copyright 2002 Mani SrivastavaCheating & PlagiarismMy apologies if you are one of the vast majority of students who don’t resort to academic dishonestybut unfortunate incident in prior years due to some bad applesWhat is cheating & plagiarism?Acting dishonestly, practicing fraudStealing or using other people’s writings or ideas•E.g. from other students, other sources such as web sites, solutions from previous offerings of this course etc.•Note that it doesn’t have to be literal copying – stealing ideas but presenting in a different style is still cheating and plagiarism.You are also guilty if you aid in cheating & plagiarismMy policy: zero toleranceHWs & design assignments: 0 points on the whole assignmentExams & quizzes: “F” grade for the course, report to DeanMore than 1 incident: : “F” grade for the course, report to Dean9Copyright 2002 Mani SrivastavaBooksEssentialDigital Integrated Circuits : A Design Perspective ; Rabaey, Jan M . Prentice Hall PTR .; The Designer's Guide To VHDL; Ashenden, Peter J . / Ashenden. Morgan Kaufmann Publishing; Helpful Principles of CMOS VLSI Design : A Systems Perspective; Weste, Neil H. E. / Eshragian, Kamran. Addison Wesley; On-line book: http://vlsi.wpi.edu/webcourse/toc.html10Copyright 2002 Mani SrivastavaLecture NotesLecture slides are your primary reference materialcontain material from places other than the textbookI will hand out copies of lecture slides3 or 6 slides to a pagePowerpoint and pdf files on the web site if you want higher resolution copies of the slidesNote that the slides are organized by topictypically, each “Lecture” will span several classes11Copyright 2002 Mani SrivastavaComputer AccountsYou need a SEASnet account (your personal account)SEASnet will allocate you extra disk space if you are registered for this courseIf you don’t have one, get one immediatelySEAS students: http://www.seas.ucla.edu/acctappNon-SEAS students: SEASnet office 2567 BoelterThis class requires CAD tools that are available only on sunugrad.seas.ucla.edu, and function only under X11you need to remotely login to sunugrad.seas.ucla.edu from a computer that has X11 serverE.g. from home/dormitory:–FAST connection (DSL, cable modem, ethernet)–Linux or equivalent with X11 environmentor, Windows with X11 server software (e.g. eXceed, X-Win32)12Copyright 2002 Mani SrivastavaCourse on the InternetCourse home page: lectures, handouts etc.http://www.ee.ucla.edu/~mbs/courses/ee116b/2002wTo save trees,
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