Clocking & TimingThe Clock Skew ProblemDelay of Clock WireConstraints on SkewClock Constraints in Edge Triggered LogicPositive and Negative SkewClock Skew in Master-Slave 2-Phase DesignClock Skew in 2-Phase DesignHow to Counter Clock Skew?Clock DistributionClock Network with Distributed BufferingExample: DEC Alpha 21164PowerPoint PresentationClock Skew in Alpha ProcessorSelf-timed and Asynchronous DesignSelf-timed Pipelined DatapathCompletion Signal GenerationSlide 18Completion Signal Using DCVSL LogicSelf-timed AdderHand-shaking ProtocolEvent Logic: the Muller C-Element2-phase Handshake ProtocolExample: Self-timed FIFO4-phase Handshake Protocol (or, RTZ)4-phase Handshake Protocol (Implementation)Asynchronous-Synchronous InterfaceA Simple SynchronizerSynchronizer: Output TrajectoriesSimulated Trajectory vs. One Pole ModelMean Time to FailureExampleCascaded Synchronizers Reduce MTFArbitersSynchronization at System LevelSkew of Local Clocks vs. ReferencePhase-Locked Loop Based Clock GeneratorRing OscillatorExample of PLL-generated ClockMani SrivastavaUCLA - EE [email protected] & TimingEE116B (Winter 2000): Lecture # 18 March 9, 1999Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]The Clock Skew ProblemCL1R1CL2R2CL3R3In Outt’t’’t’’’tl,mintl,maxtr,mintr,maxtiClock Edge Timing Depends upon PositionClock Rates as High as 500 Mhz in CMOS!Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Delay of Clock WireCLrcRSr = 0.07 /q, c = 0.04 fF/m2(Tungsten wire)Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Constraints on SkewR1 R2’’’tr,min + tl,min + ti(a) Race between clock and data. R1 R2’’’+ Ttr,max + tl,max + ti(b) Data should be stable before clock pulse is applied.t’t’’ = t’ + t’t’’ + T =datadata’’ t’ + TCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Clock Constraints in Edge Triggered Logictr mintitl min+ +T tr maxtitl max–+ +Maximum Clock Skew Determined by Minimum Delay between LatchesMinimum Clock Period Determined by Maximum Delay between LatchesCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Positive and Negative SkewR CL R CL RDataCLR CL R CL RDataCL(a) Positive skew(b) Negative skewCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Clock Skew in Master-Slave2-Phase DesignM1CL1 CL2 CL3InS1S2S3M2M3’’Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Clock Skew in 2-Phase Designclock period T TTTT  T 121’clockoverlapnew data applied to CL2previous data latched into M2tmin >  - T12tmax T  TCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]How to Counter Clock Skew?REGREGREG.REGlogOutInClock DistributionPositive SkewNegative SkewData and Clock RoutingCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Clock DistributionCLOCKH-Tree NetworkObserve: Only Relative Skew is ImportantCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Clock Network with Distributed BufferingModuleModuleModuleModuleModuleModuleCLOCKmain clock driversecondary clock driversReduces absolute delay, and makes Power-Down easierSensitive to variations in Buffer DelayLocal AreaCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Example: DEC Alpha 21164Clock frequency: 300MHz9.3 Million transistorsTotal clock load: 3.75 nFPower in clock distribution network: 20Wout of 50WUses two level clock distributionsingle 6-stage buffer at the center of the chipsecondary buffers drive left and right side clock grid in Metal3 and Metal4Total driver size: 58 cm !Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Clock DriversCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Clock Skew in Alpha ProcessorCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Self-timed and Asynchronous DesignFunctions of clock in synchronous designacts as completion signalensures the correct ordering of eventsTruly asynchronous designcompletion is ensured by careful timing analysisordering of events is implicit in logicSelf-timed designcompletion ensured by a completion signalordering imposed by handshaking protocolCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Self-timed Pipelined DatapathR2OutF2IntpF2Start DoneR1 F1tpF1Start DoneR3 F3tpF3Start DoneReq Req Req ReqAck Ack Ack ACKHS HS HSCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Completion Signal GenerationLOGICNETWORKDELAY MODULEInOutStartDoneUsing Delay Element (e.g. in memories)Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Completion Signal GenerationUsing Redundant Signal EncodingCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Completion Signal UsingDCVSL LogicPDNB0PDNIn1In1In2In2B1StartStartVDDVDDDoneB0B1Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Self-timed AdderP0C0P1G0P2G1P3G2G3VDDStartStartP0C0P1K0P2K1P3K2K3VDDStartStartC0C1C2C3C4C4C4C0C1C2C3C4VDDStartC4C3C2C1C4C3C2C1StartDone(a) Differential carry generation(b) Completion signalCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Hand-shaking ProtocolReqAckDataSENDERRECEIVERSenders actionReceivers actionReqAckDatacycle 1 cycle 2¿