Mani SrivastavaUCLA - EE [email protected] for TestEE116B (Winter 2001): Lecture # 6Copyright 2001  Mani Srivastava2VLSI Realization ProcessDetermine requirementsWrite specificationsDesign synthesis and VerificationFabricationManufacturing testChips to customerCustomer’s needTest development[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]Copyright 2001  Mani Srivastava3Definitionsn Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes.n Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function.n Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]Copyright 2001  Mani Srivastava4Validation and Test of Manufactured Circuitsn Goals of Design-for-Test (DFT)F make testing of manufactured part swift & comprehensiven DFT mantraF provide controllability and observabilityn Components of DFT strategyF provide circuitry to enable testF provide test patterns that guarantee reasonable coverage[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2001  Mani Srivastava5Test Classificationn Diagnostic testF used in chip/board debuggingF defect localizationn “Go/no-go” or production testF used to determine whether a chip is functionalF simpler than diagnostic test; must be simple & swiftn Parametric test (static/dc and dynamic/ac tests)F x ε [v,i] versus x ε [0,1]F check parameters such as NM, Vt, tp, T[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2001  Mani Srivastava6Verification vs. Testn Verifies correctness of design.n Performed by simulation, hardware emulation, or formal methods.n Performed once prior to manufacturing.n Responsible for quality of design.n Verifies correctness of manufactured hardware.n Two-part process:u 1. Test generation: software process executed once during designu 2. Test application: electrical tests applied to hardwaren Test application performed on every manufactured device.n Responsible for quality of devices. [Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]Copyright 2001  Mani Srivastava7Why such a big deal?n High speed testers are astronomically costly!n Reducing test time can help increase throughput of testerF impacts testing costn Testing must be considered from early phases of the design processCopyright 2001  Mani Srivastava8Costs of Testingn Design for testability (DFT)u Chip area overhead and yield reductionu Performance overheadn Software processes of testu Test generation and fault simulationu Test programming and debuggingn Manufacturing testu Automatic test equipment (ATE) capital costu Test center operational cost [Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]Copyright 2001  Mani Srivastava9Design for Testability (DFT)DFT refers to hardware design styles or addedhardware that reduces test generation complexity.Motivation: Test generation complexity increasesexponentially with the size of the circuit.Logicblock ALogicblock BPIPOTestinputTestoutputInt.busExample: Test hardware applies tests to blocks Aand B and to internal bus; avoids test generationfor combined A and B blocks.[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]Copyright 2001  Mani Srivastava10Present and FutureTransistors/sq. cm 4 - 10M 18 - 39MPin count 100 - 900 160 - 1475Clock rate (MHz) 200 - 730 530 - 1100Power (Watts) 1.2 - 61 2 - 96Feature size (micron) 0.25 - 0.15 0.13 - 0.101997 -2001 2003 - 2006* SIA Roadmap, IEEE Spectrum, July 1999[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]Copyright 2001  Mani Srivastava11Cost of Manufacturing Testing in 2000ADn 0.5-1.0GHz, analog instruments,1,024 digital pins: ATE purchase priceu = $1.2M + 1,024 x $3,000 = $4.272Mn Running cost (five-year linear depreciation)u = Depreciation + Maintenance + Operationu = $0.854M + $0.085M + $0.5Mu = $1.439M/yearn Test cost (24 hour ATE operation)u = $1.439M/(365 x 24 x 3,600)u = 4.5 cents/second[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]Copyright 2001  Mani Srivastava12Roles of Testingn Detection: Determination whether or not the device under test (DUT) has some fault.n Diagnosis: Identification of a specific fault that is present on DUT.n Device characterization: Determination and correction of errors in design and/or test procedure.n Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT.[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]Copyright 2001  Mani Srivastava13Design for TestabilityM state regsN inputsK outputsK outputsN inputsCombinationalLogicModuleCombinationalLogicModule(a) Combinational function(b) Sequential engine2N patterns 2N+M patternsExhaustive test is impossible or unpractical(consider a processor with N=64, M=50 at 1 µsec/pattern)[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2001  Mani Srivastava14Testing Approachn Exhaustive testing has redundancyF same fault covered by many input patterns– only one needed, other are superfluousn Cost of detecting all patterns may not be worth itF typical test procedures attempt 95-99% coverageCopyright 2001  Mani Srivastava15Ideal vs. Real Testsn Ideal tests detect all defects produced in the manufacturing process.n Ideal tests pass all functionally good devices.n Very large numbers and varieties of possible defects need to be tested.n Difficult to generate tests for some real defects. Defect-oriented testing is an open problem.n Based on analyzable fault models, which may not map on real defects.n Incomplete coverage of modeled faults due to high complexity.n Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss.n Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]Copyright 2001  Mani Srivastava16Testing as Filter ProcessFabricatedchipsGood chipsDefective chipsProb(good) = yProb(bad) = 1- yProb(pass test) = highProb(fail test) = highProb(fail test) = lowProb(pass test) =