Mani B. SrivastavaUCLA - EEVHDL: A Tutorial!2mbsOUTLINEn Introduction to the language- simple examplesn VHDL’s model of a system- its computation model: processes, signals and timen Language featuresn VHDL for logic and queue simulation3mbsWHAT IS VHDL?Programming Language + Hardware Modelling LanguageIt has all of the following:- Sequential Procedural language: PASCAL and ADA like- Concurrency: statically allocated network of processes- Timing constructs- Discrete-event simulation semantics- Object-oriented goodies: libraries, packages, polymorphism4mbsA NAND Gate Example-- black-box definition (interface)entity NAND isgeneric ( Tpd : time := 0 ns );port ( A, B : in bit; Y : out bit );end entity;-- an implementation (contents)architecture BEHAVIOR_1 of NAND isbeginY <= A nand B after Tpd;end BEHAVIOR_1;Important Conceptsentityarchitecturegenericportwaveform assignmentABY5mbsAnother Implementation of NAND-- there can be multiple implementationsarchitecture BEHAVIOR_2 of NAND issignal X : bit;begin-- concurrent statementsY <= X after Tpd;X <= ‘1’ when A=’0’ or B=’0’ else‘0’;end BEHAVIOR_2;Important Conceptsmultiple architecturessignalconcurrent statementsABY6mbsYet More NAND Gates!!!entity NAND_N isgeneric ( N : integer := 4; Tpd : time);port ( A, B : in bit_vector(1 to N);Y : out bit_vector(1 to N));end NAND_N;architecture BEHAVIOR_1 of NAND_N isbeginprocessvariable X : bit_vector(1 to N);beginX := A nand B;Y <= X after Td;wait on A, B;end process;end BEHAVIOR_1;Important Conceptsprocessvariablewaitsequential statementsevents7mbsThe process Statement[label:] process [(sensitivity_list)][declarations]begin{sequential_statement}end process [label];• It defines an independent sequential process which repeatedly executes its body.• Following are equivalent:process (A,B) processbegin beginC <= A or B; C <= A or B;end; wait on A, B;end;•No wait statements allowed in the body if there is a sensitivity_list.8mbsThe wait Statementwait [on list_of_signals][until boolean_expression][for time_expression] ;This is the ONLY sequential statement during which time advances!examples:-- wait for a rising or falling edge on CLKwait on CLK;wait until CLK’EVENT; -- this is equivalent to the above-- wait for rising edge of CLKwait on CLK until CLK=’1’;wait until CLK=’1’; -- this is equivalent to the above-- wait for 10 nswait until 10 ns;-- wait for ever (the process effectively dies!)wait;9mbsA Simple Producer-Consumer Exampleentity producer_consumer isend producer_comsumer;architecture two_phase of producer_consumer issignal REQ, ACK : bit;signal DATA : integer;beginP: process beginDATA <= produce();REQ <= not REQ;wait on ACK;end P;C: process beginwait on REQ;consume(DATA);ACK <= not ACK;end C; end two_phase;P CDATAREQACK10mbsProducer-Consumer contd. : 4-ϕ casearchitecture four_phase of producer_consumer issignal REQ, ACK : bit := ‘0’;signal DATA : integer;beginP: process beginDATA <= produce();REQ <= ‘1’;wait until ACK=’1’;REQ <= ‘0’;wait until ACK=’0’;end P;C: process beginwait until REQ=’1’;consume(DATA);ACK <= ‘1’;wait until REQ=’0’;ACK <= ‘0’;end C; end four_phase;P CDATAREQACK11mbsMuller C-Elemententity MULLER_C_ELEMENT isport (A,B : in bit; C : out bit);end MULLER_C_ELEMENT;architecture BEHAVIOR isbeginprocess beginwait until A=’1’ and B=’1’;C <= ‘1’;wait until A=’0’ and B=’0’;C <= ‘0’;end process;end BEHAVIOR;CABCCould have written:wait until A=B;C <= A;12mbsAn Edge-Triggered D Flip-Flopentity DFF isgeneric (T_setup, T_hold, T_delay : time:=0 ns);port (D, CLK: in bit; Q : out bit);begin-- check setup timeassert not (CLK’EVENT and CLK=’1’ andD’LAST_EVENT < T_setup)report “Setup violation”severity WARNING;-- check hold timeassert not (CLK’DELAYED(T_hold)’EVENT and CLK’DELAYED(Thold)=’1’ andD’LAST_EVENT < T_hold)report “Hold violation”severity WARNING;end DFF;architecture BEHAVIOR of DFF isbeginprocess beginwait on CLK until CLK=’1’;Q <= D after T_delay;end process;end BEHAVIOR;Try writing this in THOR!13mbsBehavior vs Structure DescriptionAn entity can be described by its behavior or by its structure, or in a mixed fashion.example: a 2-input XOR gateABYY = A.B+A.BABYG1G2G4G3entity XOR isport ( A,B : in bit; Y : out bit);end XOR;architecture BEHAVIOR of XOR isbeginY <= (A and not B) or (not A and B);end BEHAVIOR;architecture STRUCTURE of XOR iscomponent NANDport ( A, B : in bit; Y : out bit);end component;signal C, D, E : bit;beginG1 : NAND port map (A, B, C);G2 : NAND port map(A => A, B => C, Y => D);G3 : NAND port map(C, B => B, Y => E);G4 : NAND port map (D, E, Y);end STRUCTURE;architecture MIXED of XOR iscomponent NAND port ( A, B : in bit; Y : out bit);end component;signal C, D, E : bit;beginD <= A nand C;E <= C nand B;G1 : NAND port map (A, B, C);G4 : NAND port map (D, E, Y);end MIXED;Component Instantiation is just another Concurrent Statement!14mbsThe Generate StatementUsed to generate iteratively or conditionally a set of concurrent statements.example: a ripple-carry adderentity RIPPLE_ADDER isport (A, B : in bit_vector; CIN : in bit;SUM : out bit_vector; COUT : out bit);beginassert A’LENGTH=B’LENGTH and A’LENGTH=SUM’LENGTHreport “Bad port connections”severity ERROR;end;architecture STRUCTURE of RIPPLE_ADDER isalias IN1 : bit_vector(0 to A’LENGTH-1) is A;alias IN2 : bit_vector(0 to A’LENGTH-1) is B;alias S : bit_vector(0 to A’LENGTH-1) is SUM;signal C : bit_vector(IN1’RANGE);component FULL_ADDER port (A,B,CIN: in bit; S, COUT: out bit);end component;beginL1: for I in S’RANGE generateL2: if I=0 generateFA1: FULL_ADDERport map (IN1(0),IN2(0),CIN,S(0),C(0));end generate;L3: if I>0 generateFA2: FULL_ADDERport map (IN1(I),IN2(I),C(I-1),S(I),C(I));end generate;end generate;COUT <= C(C’HIGH);end STRUCTURE;15mbsn Concurrent StatementsProcess independent sequential processBlock groups concurrent statementsConcurrent Procedure convenient syntax forConcurrent Assertion commonly occurring formConcurrent Signal Assignment of processesComponent Instantiation structure decompositionGenerate Statement regular descriptionOrder of execution is not defined!n Sequential StatementsWait synchronization of processesAssertionSignal AssignmentVariable AssignmentProcedure CallIfCaseLoop (for, while)Next ExitReturnNullConcurrent vs Sequential Statements16mbsVHDL’s Model of a System• Static network of concurrent processes communicating using