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UCLA EE 116B - Clocking & Timing

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3/9/001Mani SrivastavaUCLA - EE [email protected] & TimingEE116B (Winter 2000): Lecture # 18 March 9, 1999Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]The Clock Skew ProblemCL1R1CL2R2CL3R3In Outφtφ’tφ’’tφ’’’tl,mintl,maxtr,mintr,maxtiClock Edge Timing Depends upon PositionClock Rates as High as 500 Mhz in CMOS!3/9/002Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Delay of Clock WireCLrcRSr = 0.07 Ω/q, c = 0.04 fF/µm2(Tungsten wire)Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Constraints on SkewR1R2φ’ φ’’δtr,min + tl,min + ti(a) Race between clock and data. R1R2φ’ φ’’+ Tδtr,max + tl,max + ti(b) Data should be stable before clock pulse is applied.tφ’tφ’’ = tφ’ + δtφ’tφ’’ + T =datadata φ’’ tφ’ + T + δ3/9/003Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Clock Constraints in Edge Triggered Logicδtrmin,titlmin,++≤Ttrmax,titlmax,δ–++≥Maximum Clock Skew Determined by Minimum Delay between LatchesMinimum Clock Period Determined by Maximum Delay between LatchesCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Positive and Negative SkewR CL R CL RDataφCLR CL R CL RDataCLφ(a) Positive skew(b) Negative skew3/9/004Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Clock Skew in Master-Slave2-Phase DesignM1CL1 CL2 CL3Inφ2S1S2S3M2M3φ1φ1φ2’φ1’Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Clock Skew in 2-Phase Designclock period T δTφ1Tφ12Tφ2Tφ21δ − Tφ12φ1φ2φ1’clockoverlapnew data applied to CL2previous data latched into M2tmin > δ - Tφ12tmax > T + δ − Tφ123/9/005Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]How to Counter Clock Skew?RE GφREGφREGφ.REGφlogOutInClock DistributionPositive SkewNegative SkewData and Clock RoutingCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Clock DistributionCLOCKH-Tree NetworkObserve: Only Relative Skew is Important3/9/006Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Clock Network with Distributed BufferingModuleModuleModuleModuleModuleModuleCLOCKmain clock driversecondary clock driversReduces absolute delay, and makes Power-Down easierSensitive to variations in Buffer DelayLocal AreaCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Example: DEC Alpha 21164n Clock frequency: 300MHzn 9.3 Million transistorsn Total clock load: 3.75 nFn Power in clock distribution network: 20WF out of 50Wn Uses two level clock distributionF single 6-stage buffer at the center of the chipF secondary buffers drive left and right side clock grid in Metal3 and Metal4n Total driver size: 58 cm !3/9/007Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Clock DriversCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Clock Skew in Alpha Processor3/9/008Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Self-timed and Asynchronous Designn Functions of clock in synchronous designF acts as completion signalF ensures the correct ordering of eventsn Truly asynchronous designF completion is ensured by careful timing analysisF ordering of events is implicit in logicn Self-timed designF completion ensured by a completion signalF ordering imposed by handshaking protocolCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Self-timed Pipelined DatapathR2OutF2IntpF2Start DoneR1 F1tpF1Start DoneR3 F3tpF3Start DoneReq Req Req ReqAck Ack Ack ACKHS HS HS3/9/009Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Completion Signal GenerationLOGICNETWORKDELAY MODULEInOutStartDoneUsing Delay Element (e.g. in memories)Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Completion Signal GenerationUsing Redundant Signal Encoding3/9/0010Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Completion Signal UsingDCVSL LogicPDNB0PDNIn1In1In2In2B1StartStartVDD VDDDoneB0B1Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Self-timed AdderP0C0P1G0P2G1P3G2G3VDDStartStartP0C0P1K0P2K1P3K2K3VDDStartStartC0C1C2C3C4C4C4C0C1C2C3C4VDDStartC4C3C2C1C4C3C2C1StartDone(a) Differential carry generation(b) Completion signal3/9/0011Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Hand-shaking ProtocolReqAckDataSENDERRECEIVERSenders actionReceivers actionReqAckDatacycle 1 cycle 2¿ ¿¡¬(a) Sender-receiver configuration(b) Timing diagram Two-Phase HandshakeCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Event Logic: the Muller C-ElementCABFA BFn+1001101010FnFn1(a) Schematic (b) Truth tableVDDFABQSRABFStaticDynamic3/9/0012Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]2-phase Handshake ProtocolCSenderlogicReceiverlogicDataData ReadyReqAckData AcceptedHandshake logicCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Example: Self-timed FIFOC CR1InOutEnAckiReqiR2 R3CReq0AckoDone3/9/0013Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]4-phase Handshake Protocol(or, RTZ)Sender’s ActionReceiver’s ActionReqAckDatacycle 1cycle 2¿ ¿¡¬ÐƒCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]4-phase Handshake Protocol (Implementation)CSenderlogicReceiverlogicDataData


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