1/15/001Mani SrivastavaUCLA - EE [email protected] TechnologyEE116B (Winter 2000): Lecture #3 January 18, 2000Copyright 2000  Mani SrivastavaReading for this Lecturen Sections 3.1, 3.2.1-3.2.3, and 3.3.1of Weste’s bookCopyright 2000  Mani SrivastavaSilicon Semiconductor Technologyn Pure silicon is a semiconductorF bulk electrical resistance in between that of a conductor and insulatorn Conductivity of silicon can be varied several orders of magnitude by introducing impurity atomsF called dopantsF acceptors: accept electrons to leave holes in silicon– lead to p-type silicon (e.g. Boron)F donors: provide electrons to silicon– lead to n-type silicon (e.g. Arsenic, Phosphorous)1/15/002Copyright 2000  Mani SrivastavaCMOS Process[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]n Semiconductor devices formed by bringing together n & p type silicon to form junctions in certain physical structuresCopyright 2000  Mani SrivastavaHow is CMOS built?n Start with a disk of silicon called waferF 75 mm to 230 mm in diameter, < 1 mm thickF cut from ingots of single-crystal silicon – pulled from a crucible of pure molten polycrystalline silicon using a seed crystaln Layers of diffusion, polysilicon, and Aluminum separated by insulating materialCopyright 2000  Mani SrivastavaOxidationn Silicon Dioxide (SiO2) important to silicon ICsF therefore, its reliable manufacturing importantn Oxidation of silicon achieved by heating silicon wafers in an oxidizing atmosphere (O2or H2O)F grows equally in both vertical directions1/15/003Copyright 2000  Mani SrivastavaMaking Silicon with Donor or Acceptor Impurities n EpitaxyF growing a single-crystal film on the silicon surface– silicon wafer subjected to elevated temperatures and a source of dopant materialn DepositionF evaporating dopant material into the silicon surfaceF followed by thermal cycle to drive impurities from silicon surface into the bulkn Ion ImplantationF silicon surface subjected to highly energized donor or acceptor atoms– atoms impinge silicon surface, and drive below it to form regions of varying concentrationsCopyright 2000  Mani SrivastavaConstruction of Transistorsn Depends on ability to controlF what type ⇒ dopant sourceF how many ⇒ energy, time, temperature etc.F where ⇒ using special material as “masks”of impurities are introduced into silicon waferCopyright 2000  Mani SrivastavaMasksn Masks act as barrier against doping impuritiesF ion implantation does not occur in places covered by mask, or dopant does not contact silicon surface for diffusion to take placen Commonly used mask materialsF photoresistF polysiliconF silicon dioxide (SiO2)F silicon nitride (SiN)1/15/004Copyright 2000  Mani SrivastavaExample: Oxide Maskn Key idea:F SiO2 surface is covered with a photoresist which is acid resistantF photoresist is selectively polymerized by UV light, and removed in those places by a solventF exposed SiO2 is now etchedn The above is called positive resistF negative photoresist: unexposed photoresist is dissolvedn Diffraction of UV around edges of mask pattern, and alignment tolerances, limit line widthsF electron beam lithography has emerged–direct: no intermediate hardware masksCopyright 2000  Mani SrivastavaPatterning of SiO2a. bare silicon waferb. wafer with SiO2& resistc. exposing resist to UV lightd. final etched SiO2Copyright 2000  Mani SrivastavaSilicon Gate Processn Silicon also comes in a polycrystalline formF called polysilicon, or just polyF high resistance– normally doped at the same time as source/drain regionsn Used asF an interconnect in silicon ICsF gate electrode in MOS transistorsF most important: acts as a mask to allow precise definition of source and drain extension under gate– minimum gate to source/drain overlap improves circuit performance (why?)– called self-aligned process1/15/005Copyright 2000  Mani SrivastavaFabrication Steps for a Silicon Gate NMOS Transistora. patterning SiO2 layerb. gate oxidationc. patterning polysiliconCopyright 2000  Mani SrivastavaFabrication Steps for a Silicon Gate NMOS Transistor (contd.)d. implant or diffusione. contact cutsf. patterning of Aluminum layerCopyright 2000  Mani SrivastavaA Basic N-well CMOS Processa. Define the N wellb. Active mask to define where thin oxide is needed to define transistor gatesc. Channel stop implant uses p-well mask to dope p-substrate p+ in areas with no n transistors1/15/006Copyright 2000  Mani SrivastavaA Basic N-well CMOS Process (contd.)d. Photoresist is stripped, leaving SiO2/SiN sandwich defining active regions. Thick field oxide is grown where SiN is absente. Poly gate definition by covering surface with poly, and then etchingCopyright 2000  Mani SrivastavaA Basic N-well CMOS Process (contd.)f. A n+ mask is used to indicate thin-oxide and poly areas that are to be implanted n+. Also called select mask.g. More complicated source/drain structures are sometimes usedCopyright 2000  Mani SrivastavaA Basic N-well CMOS Process (contd.)h. Complement of n+ mask is used to define p+ diffusion areasi. Contact cuts are defined by etching SiO2down to surface to be contactedj. Metallization is applied, and selectively etched1/15/007Copyright 2000  Mani SrivastavaA Basic N-well CMOS Process (contd.)n Final step: the wafer is passivated, and openings to bonding pads are etched to allow for wire bondingF passivation protects the silicon surface against contaminantsCopyright 2000  Mani SrivastavaCMOS Inverter in N-well ProcessCopyright 2000  Mani SrivastavaSubstrate & Well Contactsn In N-well processu p-type substrate is connected to VSSF p+ regionsu well is connected to VDDF n+ regionsn Called:F well contactsF substrate contacts1/15/008Copyright 2000  Mani SrivastavaP-well Processn P-well processes were common in early daysF N-well is more popular nown P-well preferred where NMOS and PMOS characteristics need to be more balancedF transistor that resides in well tends to have inferior characteristics as compared to transistor in native substrate– P-well has better PMOS than a N-well processCopyright 2000  Mani SrivastavaTwin-Well Processesn Allow separate optimization of NMOS and PMOSF independent optimization of threshold voltage, body effect, gain, etc.Copyright 2000  Mani SrivastavaSilicon on Insulatorn Insulating substrate (e.g. sapphire) to improve process characteristicsn AdvantagesF no latch-up problemsF speed due