VLSI Systems DesignCourse GoalsYou will NOT learn...ScheduleMore on Lab SessionsCourse StaffCourse Staff (contd.)The TA Situation (as of Jan 3)Prerequisites & GradingCheating & PlagiarismBooksLecture NotesComputer AccountsCourse on the InternetGroups for Design AssignmentsFinal WordsQuestions?Issues & Trends in VLSI DesignThe First ComputerENIAC - the First Electronic Computer (1946)Today’s ComputersMoore’s LawEvolution in Transistor CountEvolution in ComplexityEvolution in Speed & PerformanceSony Playstation IISilicon in 2010The Design ProblemProfound Impact on the way VLSI is DesignedDesign Abstraction LevelsThe Transistor Twiddling & Rectangle Pushing ApproachDesign with CAD ToolsCan’t Ignore “Transistor Twiddling”The Old and the NewPentium IIICore-based Design: System on ChipTopics Covered in this CourseTopics Covered in this Course (contd.)Mani SrivastavaUCLA - EE [email protected] Systems DesignEE116B (Winter 2001): Lecture #1Copyright 2001  Mani Srivastava2Course GoalsMain objectiveoverview of various steps in digital CMOS VLSI design–circuit, logic, and architecture issues–design tools and techniques–engineering issues for performance, noise, testability etc.Approachlectures to present VLSI design conceptsregular homework will test you on the conceptsdesign assignments will expose you to CAD tool based VLSI designCopyright 2001  Mani Srivastava3You will NOT learn...Device physicsSemiconductor processingFancy circuitsAdvanced logicComputer architectureWriting CAD toolsAnalog VLSIVLSI using technologies other than CMOS (e.g. bipolar, GaAs etc.)Copyright 2001  Mani Srivastava4ScheduleLecturesTuTh 10-11:50AM @ Boelter 5440Discussions (supervised by TAs)Section 1: Fr 12-12:50PM @ Boelter 5252Section 2: Th 12-12:50PM @ MS 3915ALaboratory Sessions (supervised by TAs)Section 1: We 12-3:50PM @ EIV 44-110Section 2: Tu 12-3:50PM @ EIV 44-110Copyright 2001  Mani Srivastava5More on Lab SessionsThere will not be any formal “lecturing” in the labsThe purpose is to have a period of time whenyou’ve guaranteed access to computers for design assignments•SEASnet labs are very crowdedTA is present to supervise & help you with the design assignmentI can come and see everybody’s progress and explain things•Usually, I will come for an hour at the beginning of every labHowever, the four hour lab sessions are not at all enough…be prepared for spending LOTs of time on design assignments outside the regular lab sessions (44-110 EIV is closed)Coming to lab sessions is strongly encouragedotherwise you will miss important assignment related announcements and fall behind very easilyUltimately, you are responsible for timely submissionCopyright 2001  Mani Srivastava6Course StaffInstructor: Mani SrivastavaEmail: [email protected]Tel: 310-267-2098Office: 7702-B Boelter HallOffice Hours: Tu 4-5, Th 1-2Lab Office Hours: Tu 12-1, We 12-1Administrative Assistant: Leticia Marr (Letty)Email: [email protected]Tel: 310-267-1954Office: 7440-D Boelter HallHours: M-F 8-5Copyright 2001  Mani Srivastava7Course Staff (contd.)Teaching Assistant #1: Pavan KumarEmail: [email protected]Tel: (310) 206-8785Office: 5th Floor Graduate Student AreaOffice Hours: TBATeaching Assistant #2: NONE ASSIGNED YETEmail: ???Tel: ???Office: ???Office Hours: ???Copyright 2001  Mani Srivastava8The TA Situation (as of Jan 3)The EE Dept. has not assigned the two Teaching Assistants needed to staff all the discussion & lab sessions it seems we will have only one TAImpact: no discussion sectionsPlease use my office hours (or schedule appointments with me)Seek help during lecturesCopyright 2001  Mani Srivastava9Prerequisites & GradingPrerequisitesunderstanding of circuits and digital logic & systems–EE115c, EE16, some advanced digital design course (any of EE116L, EE116C, EE116D etc.)GradingFinal: 30%Midterm (1) + Surprise Quizzes: 20%Homework (2-3) 15%Lab assignment (2-4) 35%Regular attendance is mandatory. Unsatisfactory attendance andparticipation in the class (lecture, lab, discussion section) will reduceyour final score by up to 20%.Copyright 2001  Mani Srivastava10Cheating & PlagiarismMy apologies if you are one of the vast majority of students who don’t resort to academic dishonestybut unfortunate incident last year due to some bad applesWhat is cheating & plagiarism?Acting dishonestly, practicing fraudStealing or using other people’s writings or ideas•E.g. from other students, other sources such as web sites, solutions from previous offerings of this course etc.•Note that it doesn’t have to be literal copying – stealing ideas but presenting in a different style is still cheating and plagiarism.You are also guilty if you aid in cheating & plagiarismMy policy: zero toleranceHWs & design assignments: zero points on the assignmentExams & quizzes: “F” grade for the course, report to DeanMore than 1 incident: : “F” grade for the course, report to DeanCopyright 2001  Mani Srivastava11BooksEssentialDigital Integrated Circuits : A Design Perspective; Rabaey, Jan M . Prentice Hall PTR .; 11/1995; Hardcover; $89.00; The Designer's Guide To VHDL; Ashenden, Peter J . / Ashen den. Morgan Kaufmann Publishing; 10/1995; Softcover; $56.00; Helpful Principles of CMOS VLSI Design : A Systems Perspective; Weste , Neil H. E. / Eshragian, Kamran. Addison Wesley; 04/1993; Hardcover; $54.95;On-line book: http://vlsi.wpi.edu/webcourse/toc.htmlCopyright 2001  Mani Srivastava12Lecture NotesLecture slides are your primary reference materialmaterial from places other than the textbookI will hand out copies of lecture slides3 or 6 slides to a pagePowerpoint and pdf files on the web site if you want higher resolution copies of the slidesNote that the slides are organized by topictypically, each “Lecture” will span several classesCopyright 2001  Mani Srivastava13Computer AccountsYou need a SEASnet account (your personal account)SEASnet will allocate you 100MB disk space for this courseIf you don’t have one, get one immediatelySEAS students: http://www.seas.ucla.edu/acctappNon-SEAS students: SEASnet office 2567 BoelterThis class requires CAD tools that are available only on sunugrad.seas.ucla.edu, and