Design for TestValidation and Test of Manufactured CircuitsTest ClassificationWhy such a big deal?Design for TestabilityTesting ApproachProblem: Controllability & ObservabilityTest ApproachesGenerating and Validating Test-VectorsFault ModelsProblem with stuck-at model: CMOS open faultProblem with stuck-at model: CMOS short faultAutomatic Test Pattern GenerationPath SensitizationAd-hoc TestDesign-for-TestabilityScan-based TestScan-based Test: OperationPolarity-Hold SRL (Shift-Register Latch)Scan-Path RegisterScan-Path TestingBoundary Scan (JTAG or IEEE1149)Built-in Self-test (BIST)Linear-Feedback Shift Register (LFSR)Signature AnalysisBILBOBILBO ApplicationMemory Self-testMani SrivastavaUCLA - EE [email protected] for TestEE116B (Winter 2000): Lecture # 9 February 8, 2000Copyright 2000  Mani SrivastavaValidation and Test of Manufactured CircuitsGoals of Design-for-Test (DFT)make testing of manufactured part swift & comprehensiveDFT mantraprovide controllability and observabilityComponents of DFT strategyprovide circuitry to enable testprovide test patterns that guarantee reasonable coverage[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2000  Mani SrivastavaTest ClassificationDiagnostic testused in chip/board debuggingdefect localization“Go/no-go” or production testused to determine whether a chip is functionalsimpler than diagnostic test; must be simple & swiftParametric test (static/dc and dynamic/ac tests)x  [v,i] versus x  [0,1]check parameters such as NM, Vt, tp, T[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2000  Mani SrivastavaWhy such a big deal?High speed testers are astronomically costly!Reducing test time can help increase throughput of testerimpacts testing costTesting must be considered from early phases of the design processCopyright 2000  Mani SrivastavaDesign for TestabilityM state regsN inputsK outputsK outputsN inputsCombinationalLogicModuleCombinationalLogicModule(a) Combinational function(b) Sequential engine2N patterns 2N+M patternsExhaustive test is impossible or unpractical(consider a processor with N=64, M=50 at 1 sec/pattern) [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2000  Mani SrivastavaTesting ApproachExhaustive testing has redundancysame fault covered by many input patterns–only one needed, other are superfluousCost of detecting all patterns may not be worth ittypical test procedures attempt 95-99% coverageCopyright 2000  Mani SrivastavaProblem: Controllability & ObservabilityCombinational circuitscontrollable and observablerelatively easy to determine test patternsSequential circuits: have state!turn into combination circuitsor, use self-testMemory: requires complex patternsuse self-test[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2000  Mani SrivastavaTest ApproachesThree approachesAd-hoc testingScan-based testingSelf-testProblem is getting harderincreasing complexity and heterogeneous combination of modules in systems-on-a-chipadvanced packaging and assembly techniques extend problem to the board level[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2000  Mani SrivastavaGenerating and ValidatingTest-VectorsAutomatic test-pattern generation (ATPG)for given fault, determine excitation vector (called test vector) that will propagate error to primary (observable) output majority of available tools: combinational n/w onlysequential ATPG available from academic researchFault simulationdetermines test coverage of proposed test-vector setsimulates correct network in parallel with faulty networksBoth require adequate models of faults in CMOS[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2000  Mani SrivastavaFault Models01sa0sa1(output)(input)Most Popular - “Stuck - at” modelx1x2x3Z, : x1 sa1 : x1 sa0 or x2 sa0 : Z sa1Covers almost all (other) occurring faults, such asopens and shorts.[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2000  Mani SrivastavaProblem with stuck-at model: CMOS open faultx1x2x1x2ZSequential effectNeeds two vectors to ensure detection!Other options: use stuck-open or stuck-short modelsThis requires fault-simulation and analysis at the switch ortransistor level - Very expensive![Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2000  Mani SrivastavaProblem with stuck-at model: CMOS short fault‘0’‘0’‘0’‘1’CA BDABCDCauses short circuit betweenVdd and GND for A=C=0, B=1Possible approach:Supply Current Measurement (IDDQ)but: not applicable for gigascale integration [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2000  Mani SrivastavaAutomatic Test Pattern GenerationDetermine a minimum set of excitation vectors that cover a significant portion of the fault set as defined by the adopted fault modelAn approach: start form random set of patternsuse fault simulation to determine how many potential faults are detectediteratively add or remove extra vectorsFault simulationdetermines fault coveragecorrect circuit simulated in parallel with a number of faulty ones, each with a single fault–results comparedCopyright 2000  Mani SrivastavaPath SensitizationOutTechniques Used: D-algorithm, PodemGoals: Determine input pattern that makes a faultcontrollable (triggers the fault, and makes its impactvisible at the output nodes)sa011011101Fault propagationFault enabling[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2000  Mani SrivastavaAd-hoc TestInserting multiplexer improves testability I/O busMemoryProcessordataaddressI/O busMemoryProcessordataaddressselecttest[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2000  Mani SrivastavaDesign-for-TestabilityExtra hardwareno functionality other than to improve testabilitytake penalty in area and performance if observability and controllability improvedExtra I/O pinse.g. Test portmultiplex test andn ormal signals on same pinsCopyright 2000  Mani SrivastavaScan-based