Mani SrivastavaUCLA - EE [email protected] Design MethodologiesEE116B (Winter 2001): Lecture # 4Copyright 2001  Mani Srivastava2Reading for this Lecturen Chapter 11 of Rabaey’s bookCopyright 2001  Mani Srivastava3Four Phases in Creating a ChipThisLecturePreviousLectureFutureLectureCopyright 2001  Mani Srivastava4The Design ProblemSource: sematech97A growing gap between design complexity and design productivity[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2001  Mani Srivastava5Profound Impact on the way VLSI is Designedn The old way: manual transistor twiddlingF expert “layout designers”F entire chip hand-craftedF okay for small chips… but cannot design billion transistor chips in this fashionn The new way: using CAD tools at high levelF tools do the grunge work…F high levels of abstractions– synthesis from a description of the behaviorF libraries of reusable cores, modules, and cellsChip design increasingly like object-oriented software design![Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2001  Mani Srivastava6Designing a VLSIn Economic viability affected by design timen Design time affected by the efficiency ofconcept → requirements → architecture→ logic/memory → circuit → layoutn Continuous trade-off betweenF performance (speed, area, power)F size of die (hence cost of die and packaging)F time of design (hence cost of engineering & schedule)F ease of test generation and testabilityCopyright 2001  Mani Srivastava7VLSI-design Tools & Methodologiesn Goal is to reduce complexity, increase productivity, and increase chances of a working chipn Key is the use of Constraints and AbstractionsF Constraints– help automate the procedure by simplifying the problemF Abstractions– collapse detail and arrive at a simpler problem to deal withn Different design methodologies F different types of constraints and trade-offsF choice driven by economics!Copyright 2001  Mani Srivastava8Design Domainsn BehavioralF what a system doesn StructuralF how entities are connected together to perform the behaviorn Physical (geometrical)F how to build a structure that has the required connectivity to implement the prescribed behaviorCopyright 2001  Mani Srivastava9Levels of Design Abstractions for Each Design Domainn Architecturaln Algorithmicn Module or functional blockn Logicaln Switchn Circuitn Deviceetc.Copyright 2001  Mani Srivastava10Design Abstraction Levelsn+n+SGD+DEVICECIRCUITGATEMODULESYSTEM[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2001  Mani Srivastava11Design Methodologyn Design process traverses iteratively betweenbehavior, structure, and geometry abstractionsn CAD tools providing more and more automationCopyright 2001  Mani Srivastava12A More Simplified FlowCopyright 2001  Mani Srivastava13Principles of Structured Design Techniquesn Hierarchyn Regularityn Modularityn LocalityCopyright 2001  Mani Srivastava14Hierarchyn Divide and conquerF compose system from simpler widgetsn Analogy with softwareF break large programs into threads and subroutinesn Hierarchy can be there in all domainsF behavior, structural, physicaln The hierarchy in different domains may not correspondF e.g. a structural hierarchy may not map well to physicalCopyright 2001  Mani Srivastava15Example of Structural HierarchyCopyright 2001  Mani Srivastava16Example of Physical HierarchyCopyright 2001  Mani Srivastava17Example of Structural HierarchyCopyright 2001  Mani Srivastava18Example of Physical HierarchyCopyright 2001  Mani Srivastava19Repartitioning Structural Hierarchy to Fit Physical HierarchyCopyright 2001  Mani Srivastava20Regularityn Hierarchy breaks a system into submodulesF but this may not solve the complexity problemF there may not be any regularity in the subdivision– we just end up with a large # of different submodulesn Regularity as a guideF subdivide into a set of similar building blocks– e.g. RAM composed of identical cellsn Regularity means that the hierarchical decomposition of a large system should result in not only simple, but also similar blocks, as much as possibleCopyright 2001  Mani Srivastava21Regularity (contd.)n Regularity can be at all levelsF circuit: use identically sized transistorsF gate: similar gate structuresF higher level: architectures with identical processorsn Regularity helps in many waysF correct by constructionF reuse of designF simplify verification of correctnessCopyright 2001  Mani Srivastava22Circuit-level Regularity Examplen A 2-1 Muxn D-type edge triggered flipflopn One-bit full addAll designed using inverter and tristate bufferCopyright 2001  Mani Srivastava23Modularityn Condition that submodules have “well-defined” functions and interfacesF in addition to regularity and hierarchyn ‘Well-formed” modules allow their interaction with others to be “well-characterized”n Depends on the situationF e.g. in s/w a subroutine has a well-defined interface– argument list with typed variablesF e.g. in IC a well-defined physical, structural, and behavioral interface– pin position, layer, size, signal type, electrical characteristics, logic functionCopyright 2001  Mani Srivastava24Why Modularity?n Allows the design of system to be broken up with confidence that the system will work as specified when the parts are combinedn Allows team design by a number of designersn Examples:F bad use: use of transmission gates as inputs– internal signals now depend on source impedanceF bad use: use dynamic CMOS logic but fail to latch or register the inputs– timing of each module will have to be checkedCopyright 2001  Mani Srivastava25Example of Poor ModularityCopyright 2001  Mani Srivastava26Localityn Modularity provided “well-characterized” interfacesF internals of modules unimportant to exterior interface• internal details remain at the local levelF a form of “information hiding”• reduces apparent complexity of the modulen Locality ensures that connections are between neighboring modules, avoiding long-distance connectionsF Example: timing locality so that time critical operations are local• clock generation and distribution network• entire clock cycle for global signals to traverse chip• placement so that global wiring is minimizedF Analogy with software• global variables are to be avoidedCopyright 2001  Mani