CMOS TechnologyReading for this LectureHow is CMOS built?Introduce DopantsIntroduce Dopants (2)OxidationMaskingExample: oxide maskPowerPoint PresentationPolysiliconConstruction of TransistorsSimplified View of CMOS Fabrication ProcessA Basic N-well CMOS ProcessSlide 14Slide 15Slide 16Slide 17Slide 18Slide 19CMOS Inverter in N-well ProcessSubstrate & Well ContactsLatch-upLatch-up (contd.)Guard RingsP-well ProcessTwin-Well ProcessesSilicon on InsulatorCMOS Process Enhancements for Better InterconnectTwo-level Metal ProcessTwo-level metal Via/Contact GeometriesPolysilicon/Refractory Metal InterconnectCMOS Layout RulesCMOS Layout Rules (contd.)Slide 34N-well CMOS Design RulesN-well CMOS Design Rules (contd.)Slide 37Slide 38Slide 39Slide 40Slide 41CMOS Inverter in N-WellSlide 43Slide 44Merged or Abutting Substrate ContactCurt SchurgersUCLA - EE DepartmentEmail: [email protected]: 310-206-4465Copyright 2002 Mani SrivastavaCMOS TechnologyEE116B (Spring 2002): Lecture #32Copyright 2002 Mani SrivastavaReading for this Lecture[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]http://vlsi.wpi.edu/webcourse/ch02/ch02.html3Copyright 2002 Mani SrivastavaHow is CMOS built?Start with a disk of silicon called wafer75 mm to 230 mm in diameter, < 1 mm thickcut from ingots of single-crystal silicon –pulled from a crucible of pure molten polycrystalline silicon using a seed crystalDifferent processing steps and techniquesIntroduce dopantsOxidationMaskingPolysilicon4Copyright 2002 Mani SrivastavaIntroduce DopantsPure silicon is a semiconductorbulk electrical resistance in between that of a conductor and insulatorConductivity of silicon can be varied several orders of magnitude by introducing impurity atomscalled dopantsacceptors: accept electrons to leave holes in silicon–lead to p-type silicon (e.g. Boron)donors: provide electrons to silicon–lead to n-type silicon (e.g. Arsenic, Phosphorous)5Copyright 2002 Mani SrivastavaIntroduce Dopants (2) Deposition through diffusionevaporating dopant material into the silicon surfacethermal cycle: impurities diffuse deeper into materialIon Implantationsilicon surface subjected to highly energized donor or acceptor atoms–atoms impinge silicon surface, and drive below it to form regions of varying concentrationsEpitaxygrowing a single-crystal film on the silicon surface–silicon wafer subjected to elevated temperatures and a source of dopant material6Copyright 2002 Mani SrivastavaOxidationMethod 1: Heating silicon wafers in an oxidizing atmosphere (O2 or H2O)Consumes SiGrows equally in both vertical directionsMethod 2: DepositionDeposited on top of existing layers7Copyright 2002 Mani SrivastavaMaskingMasks act as barrier against e.g.ion implantationdopant deposition before diffusion (dopants do not reach surface)oxidation (O2 or H2O does not reach surface)Commonly used mask materialsphotoresistpolysiliconsilicon dioxide (SiO2)silicon nitride (SiN)8Copyright 2002 Mani SrivastavaExample: oxide maska. bare silicon waferb. oxidize waferc. deposit layer of photoresistd. expose the photoresist selectively to UV light•The drawn mask pattern determines which part is exposed•Resist polymerizes where exposed9Copyright 2002 Mani Srivastavae. unexposed resist is removed with solvent: negative resist(positive resist: exposed resist is removed) f. exposed oxide is etchedg. photoresist is washed offh. the oxide can now be used as a masking layer for ion implantationUV lithography: line width limited by diffraction and alignment tolerances, but tricks are usedElectron beam lithography has emerged: directly from digital data, but more costly and slow10Copyright 2002 Mani SrivastavaPolysiliconSilicon also comes in a polycrystalline formcalled polysilicon, or just polyhigh resistance–normally doped at the same time as source/drain regionsUsed asan interconnect in silicon ICsgate electrode in MOS transistorsmost important: acts as a mask to allow precise definition of source and drain extension under gate–minimum gate to source/drain overlap improves circuit performance (why?)–called self-aligned process11Copyright 2002 Mani SrivastavaConstruction of TransistorsDepends on ability to controlwhat type dopant source how many energy, time, temperature etc.where using special material as “masks”of impurities are introduced into silicon wafer12Copyright 2002 Mani SrivastavaSimplified View of CMOS Fabrication Process13Copyright 2002 Mani SrivastavaA Basic N-well CMOS Processa. Create oxide mask (see slide 8) using the well-maskb. Implant the N-wellc. Etch away the oxide maskd. Grow the thin oxide (gate oxide) over the entire wafere. Deposit a SiN (nitride layer) and pattern it with the mask for the active areas (n and p diffusion): defines where the transistors will be14Copyright 2002 Mani Srivastavaf. Etch away the oxide where it is exposedg. Deposit resist patterned by the well-maskh. Channel stop implants: make substrate more p+ (why?)(active areas are protected by the nitride-oxide layer)15Copyright 2002 Mani Srivastavai. Remove resist and grow field oxide (nitride protects the thin oxide)j. Etch nitridek. Deposit polysiliconl. Apply photoresist with poly-mask and etch poly16Copyright 2002 Mani Srivastavam. Use n+ mask to leave only the regions where nmos tors are wanted free (also called the select mask)n. Implant the n dopants: self-aligned process•Channel is masked from S and D by the gate•Poly is also implanted (needed to improve conductivity)o. Remove masking material17Copyright 2002 Mani SrivastavaRemark: sometimes more complex S/D structures are used(LDD: lightly doped drain)p. Complementary of n+ mask is used to define p+ areas18Copyright 2002 Mani Srivastavaq. Oxide depositionr. Apply resist using contact-mask and etch contact holeds. Deposit metal t. Apply resist using metal-mask and etch metal interconnects19Copyright 2002 Mani Srivastavau. Repeat steps q-t for multiple metal layersv. Passivate wafer (protect again environment, contaminants)w. Etch openings for bonding pads to allow for connection to the package20Copyright 2002 Mani SrivastavaCMOS Inverter in N-well Process21Copyright 2002 Mani SrivastavaSubstrate & Well ContactsIn N-well processp-type substrate is
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