UCLA EE 116B - Design for Test (28 pages)

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Design for Test



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Design for Test

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Pages:
28
School:
University of California, Los Angeles
Course:
Ee 116b - Parasitics and Interconnects

Unformatted text preview:

Design for Test EE116B Winter 2000 Lecture 9 February 8 2000 Mani Srivastava UCLA EE Department mbs janet ucla edu Copyright 2000 Mani Srivastava Validation and Test of Manufactured Circuits n Goals of Design for Test DFT F n DFT mantra F n make testing of manufactured part swift comprehensive provide controllability and observability Components of DFT strategy provide circuitry to enable test F provide test patterns that guarantee reasonable coverage F Adapted from http infopad eecs berkeley edu icdesign Copyright 1996 UCB Copyright 2000 Mani Srivastava Test Classification n Diagnostic test used in chip board debugging F defect localization F n Go no go or production test used to determine whether a chip is functional F simpler than diagnostic test must be simple swift F n Parametric test static dc and dynamic ac tests x v i versus x 0 1 F check parameters such as NM Vt tp T F Adapted from http infopad eecs berkeley edu icdesign Copyright 1996 UCB Copyright 2000 Mani Srivastava Why such a big deal n n High speed testers are astronomically costly Reducing test time can help increase throughput of tester F n impacts testing cost Testing must be considered from early phases of the design process Copyright 2000 Mani Srivastava Design for Testability N inputs N inputs Combinational K outputs K outputs Combinational Logic Logic Module Module M state regs a Combinational function 2N patterns b Sequential engine 2N M patterns Exhaustive test is impossible or unpractical consider a processor with N 64 M 50 at 1 sec pattern Adapted from http infopad eecs berkeley edu icdesign Copyright 1996 UCB Copyright 2000 Mani Srivastava Testing Approach n Exhaustive testing has redundancy F same fault covered by many input patterns only one needed other are superfluous n Cost of detecting all patterns may not be worth it F typical test procedures attempt 95 99 coverage Copyright 2000 Mani Srivastava Problem Controllability Observability n Combinational circuits controllable and



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