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UCLA EE 116B - Low Power Design

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Low Power DesignIntroductionWhy worry about power? Heat DissipationEvolution in Power DissipationWhy worry about power? PortabilityPower IssuesWhere does power go in CMOS?Dynamic Power ConsumptionDynamic Power Consumption (contd.)Power Consumption is Data DependentTransition Probabilities for Basic GatesTransition Probability of 2-input NOR GateProblem: Reconvergent FanoutHow about Dynamic Circuits?4-input NAND GateTransition Probabilities for Dynamic GatesGlitching in Static CMOSExample 1: Chain of NOR GatesExample 2: Adder CircuitHow to Cope with Glitching?Short Circuit CurrentsImpact of Rise/Fall Times on Short Circuit CurrentsShort Circuit Energy as a Function of Slope RatioStatic Power ConsumptionLeakageSub-threshold in MOSPower Analysis in SPICEDesign for Worst CaseSlide 29Metric: PowerMetric: Energy/OperationMetric: Energy/Op and Delay/OpVoltage ScalingReducing VddLower Vdd Increases DelayLowering the ThresholdTransistor Sizing for Power MinimizationTransistor Sizing for Fixed ThroughputReducing Effective CapacitanceDynamic Power ReductionBig WinsReordering InputsLow Power ArithmeticReducing the Supply Voltage: an Architectural ApproachArchitecture Trade-offs: Reference DatapathParallel DatapathPipelined DatapathA Simple Datapath: SummarySummaryMani SrivastavaUCLA - EE [email protected] Power DesignEE116B (Winter 1999): Lecture # 10 February 10, 2000Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]IntroductionPower, in addition to performance, is now a significant considerationCMOS originally a low power technologybut not any more…CMOS chips can dissipate 50 Watts!Power comers from charging and discharging capacitorsfundamental to all circuits that drive wiresCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Why worry about power?Heat DissipationDEC 21164source : arpa-estomicroprocessorpower dissipationFrightening trend: power seems to be proportional to area and frequencyCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Evolution in Power DissipationCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Why worry about power?PortabilityMultimedia TerminalsLaptop ComputersDigital Cellular TelephonyBATTERY(40+ lbs)YearNominal Capacity (Watt-hours / lb)Nickel-CadiumNi-Metal Hydride65 70 75 80 85 90 95 0 10 20 30 40 50 Rechargable LithiumExpected Battery Lifetime increaseover next 5 years: 30-40%Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Power IssuesHard to get large current into a chip50W at 2.5V is 20ACheap devicemust use plastic package in a low-cost boxno fans, so thermal resistance is high (350C/Watt)power must be under 2WPortable systemneed to carry the energy (power * time) you useenergy is heavy (20Wh/lb)lower power means less battery weightCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Where does power go in CMOS?Dynamic power consumptioncharging and discharging capacitorsShort circuit currentsshort circuit path between supply rails during switchingLeakageleaking diodes and transistorsCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Dynamic Power ConsumptionVin VoutCLEnergy/transition = CL * Vdd2Power = Energy/transition * f = CL * Vdd2 * fNeed to reduce CL, Vdd, and f to reduce power.VddNot a function of transistor sizes!Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Dynamic Power Consumption (contd.)Power = Energy/transition * transition rate = CL * Vdd2 * f01= CL * Vdd2 * P01* f= CEFF * Vdd2 * fPower Dissipation is Data DependentFunction of Switching ActivityCEFF = Effective Capacitance = CL * P01Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Power Consumption is Data DependentExample: Static 2 Input NOR GateAssume:P(A=1) = 1/2P(B=1) = 1/2P(Out=1) = 1/4P(01)= 3/4  1/4 = 3/16Then:= P(Out=0).P(Out=1)CEFF = 3/16 * CLCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Transition Probabilities for Basic GatesCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Transition Probability of 2-input NOR GateCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Problem: Reconvergent FanoutABXZReconvergenceP(Z=1) = P(B=1) . P(X=1 | B=1)Becomes complex and intractable real fastCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]How about Dynamic Circuits?MpMeVDDPDNIn1In2In3OutPower is Only Dissipated when Out=0!CEFF = P(Out=0).CLCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]4-input NAND GateExample: Dynamic 2 Input NOR GateAssume:P(A=1) = 1/2P(B=1) = 1/2P(Out=0) = 3/4Then:CEFF = 3/4 * CLSwitching Activity Is Always Higher in Dynamic CircuitsCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Transition Probabilities for Dynamic Gates Switching Activity for Precharged Dynamic GatesP01 = P0Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Glitching in Static CMOSABXCZABC 101 000XZ Unit Delayalso called: dynamic hazardsObserve: No glitching in dynamic circuitsCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Example 1: Chain of NOR Gates0 1 2 3t (nsec)0.02.04.06.0V (Volt)out1out3out5out7out2out4out6out81out1 out2 out3 out4 out5...Copyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Example 2: Adder Circuit0 5 100.02.04.0Time, nsSum Output Voltage, VoltsCinS15S1065432S1Add0 Add1 Add2 Add14 Add15S0 S1 S2 S14 S15CinCopyright 2000  Mani Srivastava[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]How to Cope with


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UCLA EE 116B - Low Power Design

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