CMOS TechnologyReading for this LectureSilicon Semiconductor TechnologyCMOS ProcessHow is CMOS built?OxidationMaking Silicon with Donor or Acceptor ImpuritiesConstruction of TransistorsMasksExample: Oxide MaskPatterning of SiO2Silicon Gate ProcessFabrication Steps for a Silicon Gate NMOS TransistorFabrication Steps for a Silicon Gate NMOS Transistor (contd.)A Basic N-well CMOS ProcessA Basic N-well CMOS Process (contd.)Slide 17Slide 18Slide 19CMOS Inverter in N-well ProcessSubstrate & Well ContactsP-well ProcessTwin-Well ProcessesSilicon on InsulatorCMOS Process Enhancements for Better InterconnectTwo-level Metal ProcessTwo-level metal Via/Contact GeometriesPolysilicon/Refractory Metal InterconnectAdvanced MetalizationMani SrivastavaUCLA - EE [email protected] TechnologyEE116B (Winter 2000): Lecture #3 January 18, 2000Copyright 2000  Mani SrivastavaReading for this LectureSections 3.1, 3.2.1-3.2.3, and 3.3.1of Weste’s bookCopyright 2000  Mani SrivastavaSilicon Semiconductor TechnologyPure silicon is a semiconductorbulk electrical resistance in between that of a conductor and insulatorConductivity of silicon can be varied several orders of magnitude by introducing impurity atomscalled dopantsacceptors: accept electrons to leave holes in silicon–lead to p-type silicon (e.g. Boron)donors: provide electrons to silicon–lead to n-type silicon (e.g. Arsenic, Phosphorous)Copyright 2000  Mani SrivastavaCMOS Process[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Semiconductor devices formed by bringing together n & p type silicon to form junctions in certain physical structuresCopyright 2000  Mani SrivastavaHow is CMOS built?Start with a disk of silicon called wafer75 mm to 230 mm in diameter, < 1 mm thickcut from ingots of single-crystal silicon –pulled from a crucible of pure molten polycrystalline silicon using a seed crystalLayers of diffusion, polysilicon, and Aluminum separated by insulating materialCopyright 2000  Mani SrivastavaOxidationSilicon Dioxide (SiO2) important to silicon ICstherefore, its reliable manufacturing importantOxidation of silicon achieved by heating silicon wafers in an oxidizing atmosphere (O2 or H2O)grows equally in both vertical directionsCopyright 2000  Mani SrivastavaMaking Silicon with Donor or Acceptor Impurities Epitaxygrowing a single-crystal film on the silicon surface–silicon wafer subjected to elevated temperatures and a source of dopant materialDepositionevaporating dopant material into the silicon surfacefollowed by thermal cycle to drive impurities from silicon surface into the bulkIon Implantationsilicon surface subjected to highly energized donor or acceptor atoms–atoms impinge silicon surface, and drive below it to form regions of varying concentrationsCopyright 2000  Mani SrivastavaConstruction of TransistorsDepends on ability to controlwhat type  dopant source how many  energy, time, temperature etc.where  using special material as “masks”of impurities are introduced into silicon waferCopyright 2000  Mani SrivastavaMasksMasks act as barrier against doping impuritiesion implantation does not occur in places covered by mask, or dopant does not contact silicon surface for diffusion to take placeCommonly used mask materialsphotoresistpolysiliconsilicon dioxide (SiO2)silicon nitride (SiN)Copyright 2000  Mani SrivastavaExample: Oxide MaskKey idea:SiO2 surface is covered with a photoresist which is acid resistantphotoresist is selectively polymerized by UV light, and removed in those places by a solventexposed SiO2 is now etchedThe above is called positive resistnegative photoresist: unexposed photoresist is dissolvedDiffraction of UV around edges of mask pattern, and alignment tolerances, limit line widthselectron beam lithography has emerged–direct: no intermediate hardware masksCopyright 2000  Mani SrivastavaPatterning of SiO2a. bare silicon waferb. wafer with SiO2 & resistc. exposing resist to UV lightd. final etched SiO2Copyright 2000  Mani SrivastavaSilicon Gate ProcessSilicon also comes in a polycrystalline formcalled polysilicon, or just polyhigh resistance–normally doped at the same time as source/drain regionsUsed asan interconnect in silicon ICsgate electrode in MOS transistorsmost important: acts as a mask to allow precise definition of source and drain extension under gate–minimum gate to source/drain overlap improves circuit performance (why?)–called self-aligned processCopyright 2000  Mani SrivastavaFabrication Steps for a Silicon Gate NMOS Transistora. patterning SiO2 layerb. gate oxidationc. patterning polysiliconCopyright 2000  Mani SrivastavaFabrication Steps for a Silicon Gate NMOS Transistor (contd.)d. implant or diffusione. contact cutsf. patterning of Aluminum layerCopyright 2000  Mani SrivastavaA Basic N-well CMOS Processa. Define the N wellb. Active mask to define where thin oxide is needed to define transistor gatesc. Channel stop implant uses p-well mask to dope p-substrate p+ in areas with no n transistorsCopyright 2000  Mani SrivastavaA Basic N-well CMOS Process (contd.)d. Photoresist is stripped, leaving SiO2/SiN sandwich defining active regions. Thick field oxide is grown where SiN is absente. Poly gate definition by covering surface with poly, and then etchingCopyright 2000  Mani SrivastavaA Basic N-well CMOS Process (contd.)f. A n+ mask is used to indicate thin-oxide and poly areas that are to be implanted n+. Also called select mask.g. More complicated source/drain structures are sometimes usedCopyright 2000  Mani SrivastavaA Basic N-well CMOS Process (contd.)h. Complement of n+ mask is used to define p+ diffusion areasi. Contact cuts are defined by etching SiO2 down to surface to be contactedj. Metallization is applied, and selectively etchedCopyright 2000  Mani SrivastavaA Basic N-well CMOS Process (contd.)Final step: the wafer is passivated, and openings to bonding pads are etched to allow for wire bondingpassivation protects the silicon surface against contaminantsCopyright 2000  Mani SrivastavaCMOS Inverter in N-well ProcessCopyright 2000  Mani SrivastavaSubstrate & Well ContactsIn N-well processp-type substrate is connected to VSSp+ regionswell is connected to VDDn+ regionsCalled:well