Design for TestVLSI Realization ProcessDefinitionsValidation and Test of Manufactured CircuitsTest ClassificationVerification vs. TestWhy such a big deal?Costs of TestingDesign for Testability (DFT)Present and FutureCost of Manufacturing Testing in 2000ADRoles of TestingDesign for TestabilityTesting ApproachIdeal vs. Real TestsTesting as Filter ProcessA Modern VLSI Device System-on-a-chip (SOC)Testing PrincipleProblem: Controllability & ObservabilityTest ApproachesGenerating and Validating Test-VectorsFault ModelingWhy Model Faults?Some Real Defects in ChipsObserved PCB DefectsCommon Fault ModelsFault ModelsSingle Stuck-at FaultFault EquivalenceEquivalence RulesEquivalence ExampleFault DominanceDominance ExampleCheckpointsClasses of Stuck-at FaultsMultiple Stuck-at FaultsTransistor (Switch) FaultsProblem with stuck-at model: CMOS open faultAnother Stuck-Open ExamplesProblem with stuck-at model: CMOS short faultAnother Stuck-Short ExampleSummary of Fault ModelsAutomatic Test Pattern GenerationExhaustive Test Pattern GenerationRandom-Pattern GenerationFault SimulationFault Simulator in a VLSI Design ProcessFault Simulation AlgorithmsSerial AlgorithmSerial Algorithm (Cont.)Parallel Fault SimulationParallel Fault Sim. ExampleConcurrent Fault SimulationConc. Fault Sim. ExampleFault SamplingMotivation for SamplingFunctional vs. Structural ATPGCarry CircuitFunctional vs. Structural (Continued)Automatic Test Pattern Generation: Path SensitizationPath Sensitization Method Circuit ExampleUsing 5-Valued LogicSlide 65Slide 66Slide 67Irredundant Hardware and Test PatternsRedundant Hardware and SimplificationRedundant Fault q sa1Multiple Fault MaskingSlide 72Ad-hoc TestDesign-for-TestabilityScan-based TestScan-based Test: OperationPolarity-Hold SRL (Shift-Register Latch)Scan-Path RegisterScan-Path TestingBoundary Scan (JTAG or IEEE1149)Built-in Self-test (BIST)Linear-Feedback Shift Register (LFSR)Signature AnalysisBILBOBILBO ApplicationMemory Self-testMani SrivastavaUCLA - EE DepartmentRoom: 7702-B Boelter HallEmail: [email protected]: 310-267-2098WWW: http://www.ee.ucla.edu/~mbsCopyright 2002  Mani SrivastavaDesign for TestEE116B (Winter 2002): Lecture # 62Copyright 2002  Mani SrivastavaVLSI Realization ProcessDetermine requirementsWrite specificationsDesign synthesis and VerificationFabricationManufacturing testChips to customerCustomer’s needTest development[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]3Copyright 2002  Mani SrivastavaDefinitionsDesign synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes.Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function.Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]4Copyright 2002  Mani SrivastavaValidation and Test of Manufactured CircuitsGoals of Design-for-Test (DFT)make testing of manufactured part swift & comprehensiveDFT mantraprovide controllability and observabilityComponents of DFT strategyprovide circuitry to enable testprovide test patterns that guarantee reasonable coverage[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]5Copyright 2002  Mani SrivastavaTest ClassificationDiagnostic testused in chip/board debuggingdefect localization“Go/no-go” or production testused to determine whether a chip is functionalsimpler than diagnostic test; must be simple & swiftParametric test (static/dc and dynamic/ac tests)x  [v,i] versus x  [0,1]check parameters such as NM, Vt, tp, T[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]6Copyright 2002  Mani SrivastavaVerification vs. TestVerifies correctness of design.Performed by simulation, hardware emulation, or formal methods.Performed once prior to manufacturing.Responsible for quality of design.Verifies correctness of manufactured hardware.Two-part process:1. Test generation: software process executed once during design2. Test application: electrical tests applied to hardwareTest application performed on every manufactured device.Responsible for quality of devices. [Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]7Copyright 2002  Mani SrivastavaWhy such a big deal?High speed testers are astronomically costly!Reducing test time can help increase throughput of testerimpacts testing costTesting must be considered from early phases of the design process8Copyright 2002  Mani SrivastavaCosts of TestingDesign for testability (DFT)Chip area overhead and yield reductionPerformance overheadSoftware processes of testTest generation and fault simulationTest programming and debuggingManufacturing testAutomatic test equipment (ATE) capital costTest center operational cost [Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]9Copyright 2002  Mani SrivastavaDesign for Testability (DFT)DFT refers to hardware design styles or addedhardware that reduces test generation complexity.Motivation: Test generation complexity increasesexponentially with the size of the circuit.Logicblock ALogicblock BPIPOTestinputTestoutputInt.busExample: Test hardware applies tests to blocks Aand B and to internal bus; avoids test generationfor combined A and B blocks.[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]10Copyright 2002  Mani SrivastavaPresent and Future Transistors/sq. cm 4 - 10M 18 - 39M Pin count 100 - 900 160 - 1475Clock rate (MHz) 200 - 730 530 - 1100Power (Watts) 1.2 - 61 2 - 96 Feature size (micron) 0.25 - 0.15 0.13 - 0.101997 -2001 2003 - 2006* SIA Roadmap, IEEE Spectrum, July 1999[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]11Copyright 2002  Mani SrivastavaCost of Manufacturing Testing in 2000AD0.5-1.0GHz, analog instruments,1,024 digital pins: ATE purchase price= $1.2M + 1,024 x $3,000 = $4.272MRunning cost (five-year linear depreciation)= Depreciation + Maintenance + Operation= $0.854M + $0.085M + $0.5M= $1.439M/yearTest cost (24 hour ATE operation)= $1.439M/(365 x 24 x 3,600)= 4.5 cents/second[Adapted from VLSI Testing Course by Bushnell/Agrawal at