Parasitics and InterconnectsImpact of Interconnect WiresDealing with ResistanceResistance EstimationSheet Resistance“Channel” ResistanceResistance of Non-rectangular ShapesResistance Considerations in LayoutProblems of Interconnect ResistanceElectromigrationElectromigration (contd.)Slide 12Resistance & Reliability - Ohmic Voltage DropResistance & Reliability - Ohmic Voltage Drop (contd.)Solutions for Ohmic-voltage DropsPower and Ground DistributionDealing with CapacitanceCapacitance EstimationThe Parallel Plate ModelTypical Wiring Capacitance ValuesFringing CapacitanceFringing Capacitance ValuesCapacitance vs. W/HInterwire CapacitanceSlide 25Impact of Interwire CapacitanceCapacitance CrosstalkCombating Capacitive CrosstalkDriving Large CapacitancesReducing the SwingPrecharged BusCharge Redistribution AmplifierBipolar vs. MOSTristate BuffersTechnology ScalingIncreased Impact of InterconnectScaling BehaviorScaling TransistorsScaling InterconnectTechnology Scaling & InterconnectNature of InterconnectTechnology Scaling & Interconnect (contd.)Wire Length Estimation via Rent’s RuleWhat can be done?Polycide Gate MOSFETModern InterconnectDealing with InductanceInductive Effects in ICsInductance & Performance - Transmission Line EffectsTransmission LineLossless Transmission Line ParametersPropagation along Loss less Transmission LineWave Propagation SpeedTerminationTransmission Line with Terminating ImpedancesWave Reflection for Different TerminationsTransmission Line Response (RL = )Lattice DiagramHandling Transmission Line EffectsOutput Buffer ModelOutput Buffer ResponseSimultaneous Switching of DriversL di/dtL di/dt SimulationSolving the Ldi/dt ProblemSolving the Ldi/dt Problem (contd.)Selecting the Right PinSlide 68Decoupling CapacitorPackagingPackaging RequirementsClassifying PackagingInterconnect LevelsWire BondingTape Automated Bonding (TAB)Flip-Chip BondingPackage-to-Board InterconnectPackage TypesTypical L & C Values of Packaging and Bonding StylesMulti-Chip ModulesWhen to consider interconnect parasitics?When to consider interconnect parasitics? (contd.)Finally...Curt SchurgersUCLA - EE DepartmentEmail: [email protected]: 310-206-4465 Copyright 2002  Mani SrivastavaParasitics and InterconnectsEE116B (Winter 2002): Lecture #72Copyright 2002  Mani SrivastavaImpact of Interconnect WiresInterconnects introduce parasitic effects that are absent in the ideal wiresaffect performance due to increase in delaysreduce reliability due to increase in noiseThe impact of these parasitics increase as devices shrink and dies get largerCauses of parasiticsResistiveCapacitiveInductive3Copyright 2002  Mani SrivastavaDealing with ResistanceEstimation and impact4Copyright 2002  Mani SrivastavaResistance EstimationResistance of a slab of conducting material isR = (/ t) * (L/W) = Rs * (L/W)where Rs = sheet resistance in  / squareFollowing have same resistances:LWWWL Ltt5Copyright 2002  Mani SrivastavaSheet ResistanceTypical values in a 1 m process are:Poly (t=0.33 m) = 10, M1/M2 = .07, Silicide = 3n+ & p+ Diffusion = 10, N-WELL = 1K to 1.5KFunction of:thicknesse.g. upper metal layers are usually thickere.g. memory processes have thinner metals to reduce vertical topology jumps to improve yieldresistivity, which in turn depends on•density of impurities (in case of poly & diffusion)•extent of chemical change (in case of silicide)6Copyright 2002  Mani Srivastava“Channel” ResistanceUseful approximation for performance estimationRc = k*(L/W) where k = 1 / Cox(Vgs-Vt) in linear regionFor both NMOS & PMOS, typical values of k are 1000 to 30000  / squareMobility  and threshold Vt depend on temperature channel resistance depends on temperature switching-time and power consumption vary tooIncrease in Rc is about +0.25% per Centigradeincrease in Rs is about +0.3% / Celsius for metal & poly, about 1% / Celsius for well diffusion7Copyright 2002  Mani SrivastavaResistance of Non-rectangular ShapesSHAPE RATIO RESISTANCEA 1 1A 5 5B 1 2.5B 1.5 2.55B 2 2.6B 3 2.75C 1.5 2.1C 2 2.25C 3 2.5C 4 2.65Measured Resistances8Copyright 2002  Mani SrivastavaResistance Considerations in LayoutMetal preferred for long interconnectsPolysilicon only for local interconnectsDiffusion (n+, p+) and poly have comparable Rshowever, diff has larger caps & associated RC delaysTransitions between layers add contact resistancetypical values min sized contacts in a 1 m process are: 21  for M1 to n+,p+, or poly; 2  for M1 to M2 avoid excess contacts & viaspossible to reduce contact resistance by making larger holes… but limited due to current crowding (current concentrates around perimeter)9Copyright 2002  Mani SrivastavaProblems of Interconnect ResistanceRC delays of the wiresSee lecture on DelayResistive (ohmic) voltage dropsRelated problem: Electromigration10Copyright 2002  Mani SrivastavaElectromigrationCurrent density (current per unit area) in a metal wire is limited due to electromigrationa direct current in a metal wire running over a long time period causes a transport of metal ions•causes wire to break or to short circuit to another wiresignal wires carry AC, and are less susceptible•bidrectional electron flow anneals crystalline structureRate of electromigration depends on:temprature, crystal structure, current density•only current density can be controlled by VLSI designersSolutions?keeping current below 0.5 to 1 mA/m helps•this can be used to determine minimal wire widthsadding alloying elements (Cu,Tu) prevents movement of Al ions11Copyright 2002  Mani SrivastavaElectromigration (contd.)Limits dc-current to 1 mA/m[from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB and Prentice hall 1995]12Copyright 2002  Mani SrivastavaElectromigration (contd.)[from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB and Prentice hall 1995]13Copyright 2002  Mani SrivastavaResistance & Reliability - Ohmic Voltage DropCurrent flowing through a resistive wire results in olhmic voltage drop that degrades signal levelsimportant in power distribution networks where current levels reach 100 mA and even amperesExample: a 15 mm long Vdd or GND wire with a current of 1 mA per m widththis is about max Al wire can sustain without electromigrationwith sheet resistance of 0.07 /square, the