EE116B : VLSI Systems Design (Mani Srivastava) Winter 20021 of 20 Design Assignment #1: Cell Layout(due by 12 Noon on 2/6/02)Group Id (see Important Note below): Name 1:______________________________________________________________________Name 2: ______________________________________________________________________Name 3: ______________________________________________________________________Total = 100 points (125 points for Groups of 3 who need to do extra work, but whose scoreswill be normalized to be out of 100 points for purposes of grading)Important Note 1: This assignment (and future design assignments) is to be done in the groupsof 2 or 3 that you have formed. Please see me immediately if you are not in a group.Important Note 2: Those groups which have three students need to do extra work. Please lookat the relevant section.Important Note 3: Late submission policy is as follows:< 24 hour delay: your score will be reduced by 50% of what you get during grading.>= 24 hour delay: you will get a score of zeroThere will be no exceptions to this rule and no extensions - please don’t bother asking me what-ever may be your reason.Please submit the assignment to the TA in the lab on the due date, or give it to my secretaryLeticia Marr (7440D Boelter), making sure to have her sign the date and time of submission onthe cover of your report.If you have a question or a problem, please first read the Frequently Asked Questions at theend.1. ObjectiveIn this assignment you have to design and characterize (i.e. transistor netlist, pre-layout circuitsimulation, layout, design rule check, extraction, post-layout circuit simulation, and post-layoutswitch-level simulation) two cells: a 2-input NAND gate and an 8-bit arithmetic unit that does 2’scomplement addition and subtraction. As explained later, your grade will be a function of the areaEE116B : VLSI Systems Design (Mani Srivastava) Winter 20022 of 20and speed of your design. In the previous lab you became familiar with Virtuoso, the layout editorin Cadence. In this assignment you will use that, together with Cadence’s schematic editor calledComposer (which allows you to create circuit schematics and is similar to schematic tools youhave seen in EE16, EE116L, EE116D etc.), and circuit simulator (Spectre, which is similar toSpice). In addition, you will also use IRSIM, which is a switch-level simulator (as opposed to acircuit level simulator). IRSIM is not a part of Cadence.Read this document very carefully before you embark on this assignment: a careful reading willprevent needless struggle. In case you need to view this document on-line, you can find a pdf copyof this document under the Lab page at the course web site http://nesl.ee.ucla.edu/courses/ee116b/2002w.2. TechnologyYou will use the HP AMOS14TB technology which is an N-well 0.6 micron, 3 metal layer, 1 polylayer, 3.3V technology. This is a process available through USC/ISI’s MOSIS design service(http://www.mosis.org) that I had mentioned. You can get information on this process throughhttp://www.mosis.org/Technical/Processes/proc-hp-amos14tb.html. You will notice from the website that the process supports three different design rules: HP_AMOS14TB, SCMOS, andSCMOS_SUBM. The first one are the more aggressive micron-based design rules, while the lattertwo are the lambda-based “scalable” (but conservative) design rules from MOSIS.SCMOS_SUBM are a version of SCMOS that take advantage of submicron processes. The tech-nology file supplied to you uses the SCMOS_SUBM design rules. The details on theSCMOS_SUBM design rules are available at http://www.mosis.org/Technical/Designrules/scmos/scmos-main.html. Read this file, and then look in Table 3b on the web page for the HPAMOS14TB entry, and follow the link SCN3M_SUBM that will take you to another table (Table6). There you will find the detailed rules in the row whose first column says SCN3M. Make sureyou use the SUBM versions of the rules.3. NCSU Cadence Design Toolkit (CDK)In this assignment we will use Cadence enhanced with a package called “Cadence Design Kit” orCDK that has been created by North Carolina State University (NCSU). The CDK provides vari-ous libraries, technology files, parameterized cells, additional menu entries, modifications to stan-dard Cadence dialog boxes, interfaces to simulators, and custom SKILL code (a language thatallows customization of Cadence tools) for a much more pleasant design experience with theMOSIS SCMOS technologies than with raw Cadence tools. If you follow the set up instructionsin section 7, you will automatically have NCSU CDK available to you. (Note: If you are curious,the package is installed at ~ee116bta/dist/NCSU. You will find the technology library that you areusing in the ~ee116bta/dist/NCSU/lib/NCSU_TechLib_hp06 directory. For example, the filedivaDRC.rul in that directory contains the design rules.)You can read about CDK at http://www.ece.ncsu.edu/cadence/CDK.html. I strongly suggest thatyou read through the README file (http://www.ece.ncsu.edu/cadence/README.html) and theUser Startup Information (http://www.ece.ncsu.edu/cadence/doc/cdsuser/GettingStarted.html).EE116B : VLSI Systems Design (Mani Srivastava) Winter 20023 of 20They, particularly the second document, contain valuable and time saving tips; not all of the infor-mation is relevant, but most of it is. Make sure to follow the links within the document. In partic-ular, do not miss MOSIS IC Layer Information (http://www.ece.ncsu.edu/cadence/doc/layerInfo.html) that describes the layers in the MOSIS processes.Finally, there is a very nice on-line document at http://vlsi.wpi.edu/cds/ from Worcester Polytech-nic Institute (WPI) that describes design in Cadence in general and using CDK features in partic-ular. The design methodology that I have described below, and which I recommend that youfollow, is based on this document.4. Layout constraintsThe cell layouts must be done using Cadence. They must be free of any design rule errors, andmust include wells and appropriate and sufficient contacts to all wells and substrate. The layoutmust be done in the following standard cell style.• The height of the standard cells is exactly 30 µm. • Standard cells are made to “abut” left and right to the same or different standard cells. • This means that power (VDD) and Ground (GND) run horizontally at the top (VDD) and bot-tom (GND) of the cell. The width is minimum 3.6 µm as shown below.• Only wells and select