A Really Rapid Review of CMOS CircuitsReading for this LecturePhysical Structure of MOS Transistors: the NMOSThe PMOS TransistorThe CMOS TechnologyThreshold Voltage ConceptCurrent-Voltage RelationsTransistor in Saturation2-D Representation of MOS TransistorSwitch-Level View of NMOS & PMOSCMOS SwitchCMOS InverterCMOS Inverter LayoutNMOS Switches in SeriesPMOS Switches in SeriesSwitches in Parallel2-Input CMOS NAND Gate: the Switch View2-Input CMOS NAND Gate: the Circuit ViewN-input CMOS NAND Gate4-Input NAND Gate2-Input CMOS OR-GateN-Input CMOS OR-GateProperties of CMOS GatesMaking Compound Gates in CMOSKey Idea in CMOS Compound Logic GatesMore on CMOS Logic StylePull-Up and Pull-Down CircuitsCMOS Compound GateWhat is this?How do we implement these?A 2-Input CMOS MultiplexerHow can one implement multiplexer using CMOS gates?Layout: the Standard Cell ApproachTwo versions of a.(b+c)Logic GraphConsistent Euler PathExample: x = ab + cdExistence of Consistent Euler PathsMemory & Storage in CMOSA CMOS Positive Level-Sensitive D LatchA CMOS Positive Edge-Triggered D RegisterPerformance Analysis of CMOS GatesMOS Transistors are not “Ideal” SwitchesCMOS Inverter: A More Detailed ViewCMOS Inverter: Steady State ResponseCMOS Inverter: Transient ResponseWhat is the value of Ron?Numerical Examples for 1.2m CMOSTransistor SizingPropagation Delay AnalysisAnalysis of Propagation DelayDesign for Worst CaseInfluence of Fan-in and Fan-out on Delaytp as a Function of Fan-inFast Complex Gates - IFast Complex gates - IIFast Complex Gates - IIIFast Complex Gates - IVExample: Full AdderRevised Full AdderMani SrivastavaUCLA - EE [email protected] A Really Rapid Reviewof CMOS CircuitsEE116B (Winter 2001): Lecture #2Copyright 2001  Mani Srivastava2Reading for this LectureReview EE115C notesRabaey CH 3, 4, and 6Copyright 2001  Mani Srivastava3Physical Structure of MOS Transistors: the NMOS[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]Copyright 2001  Mani Srivastava4The PMOS Transistor[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]Copyright 2001  Mani Srivastava5The CMOS Technology[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2001  Mani Srivastava6Threshold Voltage Conceptn+n+p-substrateDSGBVGS+-DepletionRegionn-channel[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2001  Mani Srivastava7Current-Voltage Relations[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2001  Mani Srivastava8Transistor in Saturationn+n+SGVGSDVDS > VGS - VTVGS - VT+-[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2001  Mani Srivastava92-D Representation of MOS Transistor[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2001  Mani Srivastava10Switch-Level View of NMOS & PMOS[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]Copyright 2001  Mani Srivastava11CMOS Switch[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]Copyright 2001  Mani Srivastava12CMOS Inverter[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]Copyright 2001  Mani Srivastava13CMOS Inverter LayoutPolysiliconInOutMetal1VDDGNDPMOSNMOS1.2 m=2[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2001  Mani Srivastava14NMOS Switches in Series[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]Copyright 2001  Mani Srivastava15PMOS Switches in Series[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]Copyright 2001  Mani Srivastava16Switches in Parallel[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]Copyright 2001  Mani Srivastava172-Input CMOS NAND Gate: theSwitch View[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]Copyright 2001  Mani Srivastava182-Input CMOS NAND Gate: theCircuit View[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]Copyright 2001  Mani Srivastava19N-input CMOS NAND Gate[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]Copyright 2001  Mani Srivastava204-Input NAND GateOutIn1 In2 In3 In4In3In1In2In4In1In2In3In4VDDOutGNDVDDIn1 In2 In3 In4VddGNDOut[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2001  Mani Srivastava212-Input CMOS OR-Gate[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]Copyright 2001  Mani Srivastava22N-Input CMOS OR-Gate[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]Copyright 2001  Mani Srivastava23Properties of CMOS GatesVdd and GND are never directly connectedi.e. no shortingOutput is always connected to either Vdd or GNDi.e. it never floatsCopyright 2001  Mani Srivastava24Making Compound Gates in CMOSF = ((A.B) + (C.D))[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]Copyright 2001  Mani Srivastava25Key Idea in CMOS Compound Logic GatesVDDVSSPUNPDNIn1In2In3F = GIn1In2In3PUN and PDN are Dual NetworksPMOS OnlyNMOS Only[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2001  Mani Srivastava26More on CMOS Logic Style[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2001  Mani Srivastava27Pull-Up and Pull-Down Circuits[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]Copyright 2001  Mani Srivastava28CMOS Compound Gate[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]Copyright 2001  Mani Srivastava29What is this?[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]Copyright 2001  Mani Srivastava30How do we implement these?Z = (A.B.C.D)’Z = ((A.B) + C.(A+B))’Z = A.B + A’.B’what is this?Z = A.B’.C’ + A’.B’.C + A’.C’.B + A.B.Cwhat is this?Copyright 2001  Mani Srivastava31A 2-Input CMOS MultiplexerOutput = A.S + B.S’[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]Copyright 2001  Mani Srivastava32How can one implement multiplexer using CMOS gates?Copyright 2001  Mani Srivastava33Layout: the Standard Cell ApproachVDDVSSWellsignalsRouting Channelmetal1polysilicon[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]Copyright 2001  Mani Srivastava34Two versions of a.(b+c)a c b a b cxxGNDVDDVDDGND(a)