Mani SrivastavaUCLA - EE [email protected] and InterconnectsEE116B (Winter 2001): Lecture #7Copyright 2001  Mani Srivastava2Impact of Interconnect Wiresn Interconnects introduce parasitic effects that are absent in the ideal wiresF affect performance due to increase in delaysF reduce reliability due to increase in noisen Causes of parasiticsF capacitive, resistive, inductiven Unfortunate scaling behaviorF interconnect effects increase as devices shrink• dominatant effect in submicron technologiesF production of ever larger dies increase wire lengths• aggravates the impact of interconnectsCopyright 2001  Mani Srivastava3Technology Scaling & Interconnectn Scaling technology by factor S reduces most interconnect parametersF e.g. wire width W, thickness toxn However, scaling behavior of wire lengths depends on wire localityF local, intramodule interconnectionsF global modules connecting large modulesn A typical wire length distribution shows two peaksF one around 0.1*LDF another around 0.5*LD(LD=AD0.5)Copyright 2001  Mani Srivastava4Nature of InterconnectLocal InterconnectGlobal InterconnectSLocal = STechnologySGlobal = SDie[from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB and Prentice hall 1995]Copyright 2001  Mani Srivastava5Technology Scaling & Interconnect (contd.)n Moral of the story: wire lengths scale differentlyF local wire lengths scale according to the technology scaling factor• increased packing of transistors reduce local wire lengthsF global wires grow proportional to die size• empirical formula for global wire length Lav= AD0.5/3• ever-larger dies are fabricated as material quality and manufacturing techniques improve⇒ wire lengths of global interconnects growF resulting in a growing disparity!Copyright 2001  Mani Srivastava6Dealing with ResistanceEstimation and impactCopyright 2001  Mani Srivastava7Resistance Estimationn Resistance of a slab of conducting material isR = (ρ/ t) * (L/W) = Rs* (L/W)where Rs= sheet resistance in Ω / squaren Following have same resistances:LWWWL LttCopyright 2001  Mani Srivastava8Sheet Resistancen Typical values in a 1 µm process are:Poly (t=0.33 µm) = 10, M1/M2 = .07, Silicide = 3n+ & p+ Diffusion = 10, N-WELL = 1K to 1.5Kn Function of:F thicknesse.g. upper metal layers are usually thickere.g. memory processes have thinner metals to reduce vertical topology jumps to improve yieldF resistivity, which in turn depends on• density of impurities (in case of poly & diffusion)• extent of chemical change (in case of silicide)Copyright 2001  Mani Srivastava9“Channel” Resistancen Useful approximation for peformance estimationRc= k*(L/W) where k = 1 / µCox(Vgs-Vt) in linear regionn For both NMOS & PMOS, typical values of k are 1000 to 30000 Ω / squaren Mobility µ and threshold Vtdepend on temperature⇒ channel resistance depends on temperature⇒ switching-time and power consumption vary toon Increase in Rcis about +0.25% per CentigradeF increase in Rsis about +0.3% / Celsius for metal & poly, about 1% / Celsius for well diffusionCopyright 2001  Mani Srivastava10Resistance of Non-rectangular Shapesn Non-rectangular shapes: corners, odd shaped transistorsn One method: break into simple regionsWLL L LWW1W2W1W2R=L/WR=L/W R=4L/(L+4W1) R=2L/(L+2W1)Copyright 2001  Mani Srivastava11Resistance of Non-rectangular Shapes (contd.)SHAPE RATIO RESISTANCEA 1 1A 5 5B 1 2.5B 1.5 2.55B 2 2.6B 3 2.75C 1.5 2.1C 2 2.25C 3 2.5C 4 2.65Measured ResistancesCopyright 2001  Mani Srivastava12Resistance Considerations in Layoutn Metal preferred for long interconnectsn Polysilicon only for local interconnectsn Diffusion (n+, p+) and poly have comparable RsF however, diff has larger caps & associated RC delaysn Transitions between layers add contact resistanceF typical values min sized contacts in a 1 µm process are: 21 Ω for M1 to n+,p+, or poly; 2 Ω for M1 to M2⇒ avoid excess contacts & viaspossible to reduce contact resistance by making larger holes… but limited due to current crowding(current concentrates around perimeter)Copyright 2001  Mani Srivastava13Effect of Technology Scalingn Full scaling (i.e. scale all dimensions) increases the sheet resistance due to reduction in thicknessn Resistance of local interconnects grows linearly with scaling factor s (<1)R = (ρ/s t) * (sL/sW) = Rs/sn Situation worse for global interconnects because their length tends to grow (scale as 1/s)n Multiple problems:F increasing RC delaysF increasing resistive (ohmic) voltage dropsCopyright 2001  Mani Srivastava14What can be done?n Selective scaling … i.e. keep thickness constantF makes process more complexF negative impact on interconnect capacitanceincreased fringe capacitance and interwire capacitancen Interconnect materials with lower sheet resistanceF e..g. silicides, coppern Multiple interconnect layersF tends to reduce wire lengths– straight connections between two points become feasible due to fewer obstacles– overall area is reduced since wires can go over gatesF upper layers (thicker, wider) for global interconnectsCopyright 2001  Mani Srivastava15Polycide Gate MOSFETn+n+SiO2PolySiliconSilicidepSilicides: WSi2, TiSi2, PtSi2 and TaSiConductivity: 8-10 times better than Poly[from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB and Prentice hall 1995]Copyright 2001  Mani Srivastava16Modern Interconnect[from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB and Prentice hall 1995]Copyright 2001  Mani Srivastava17Electromigrationn Current density (current per unit area) in a metal wire is limited due to electromigrationF a direct current in a metal wire running over a long time period causes a transport of metal ions• causes wire to break or to short circuit to another wireF signal wires carry AC, and are less susceptible• bidrectional electron flow anneals crystalline structuren Rate of electromigration depends on:F temprature, crystal structure, current density• only current density can be controlled by VLSI designersn Solutions?F keeping current below 0.5 to 1 mA/µm helps• this can be used to determine minimal wire widthsF adding alloying elements (Cu,Tu) prevents movement of Al ionsCopyright 2001  Mani Srivastava18Electromigration (contd.)Limits dc-current to 1 mA/µm[from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB and Prentice hall 1995]Copyright 2001  Mani Srivastava19Electromigration