Review CMOS Logic Gates Acknowledgment These notes are updated from Prof Mason s notes INV Schematic NOR Schematic Vsg x pMOS Vout Vin Vin NAND Schematic x y g x y x y Vgs nMOS CMOS inverts functions CMOS Combinational Logic g x y x y y x x parallel for OR series for AND use DeMorgan relations to reduce functions remove all NAND NOR operations implement nMOS network create pMOS by complementing operations AOI OAI Structured Logic XOR XNOR using structured logic ECE 410 Prof F Salem Spring 2009 Lecture Notes Page 3 1 1 Review XOR XNOR and TGs Exclusive OR XOR a b a b a b Exclusive NOR b b a a a b a b a b Transmission Gates XOR XNOR in AOI Form y x s for s 1 MUX Function using TGs F Po s P1 s ECE 410 Prof F Salem Spring 2009 Lecture Notes Page 3 2 2 Integrated Circuit Layers Integrated circuits are a stack of patterned layers metals good conduction used for interconnects was Al now copper insulators silicon dioxide block conduction semiconductors silicon conducts under certain conditions Polysilicon resistive element forms tx gates Stacked layers form 3 dimensional structures silicon Multi layer metals silicon dioxide background assumed to be silicon covered by silicon dioxide ECE 410 Prof F Salem Spring 2009 Lecture Notes Page 3 3 3 Interconnect Parasitics Parasitic unwanted natural electrical elements Metal Resistance metals have a linear resistance and obey Ohm s law V IR generate parasitic interconnect resistance Rline Rline l A A wt l A resistivity conductivity t w l defined by sheet resistance Rs 1 resistance per unit square ohms t t Rline Rs when l w Rline Rs l Rs determined by process l w by designer w ECE 410 Prof F Salem Spring 2009 Lecture Notes Page 3 4 4 Metal Resistance Measuring squares From top view of layout can determine how many squares of the layer are present square is a unit length equal to the width w w n 8 l Rline Rs n where n l is the number of squares w Get a unit of resistance Rs for each square n ECE 410 Prof F Salem Spring 2009 Lecture Notes Page 3 5 5 Parasitic Line Capacitances Capacitor Basics Q CV C in units of Farads F I C dV dt Parallel plate capacitance Cline ox w l F w l Area tox ox permittivity of oxide RC time constant of an interconnect line Rline Cline ECE 410 Prof F Salem Spring 2009 Lecture Notes Page 3 6 6 Intrinsic Silicon Properties Read textbook section 3 2 1 3 2 2 3 2 3 Won t have time to cover this in detail in lecture but it s important to understanding how transistors work We ll cover some more of the physics later on Intrinsic Semiconductors undoped i e not n or p silicon has intrinsic charge carriers electron hole pairs are created by thermal energy intrinsic carrier concentration ni 1 45x1010 cm 3 at room temp function of temperature increase or decrease with temp n p ni in intrinsic undoped material n number of electrons p number of holes mass action law np ni2 applies to undoped and doped material ECE 410 Prof F Salem Spring 2009 Lecture Notes Page 3 7 7 Extrinsic Silicon Properties doping adding dopants to modify material properties n type n add elements with extra an electron arsenic As or phosphorus P Group V elements nn concentration of electrons in n type material nn Nd cm 3 Nd concentration of donor atoms pn concentration of holes in n type material n p defines region Nd pn ni2 using mass action law as heavily doped always a lot more n than p in n type material p type p add elements with an extra hole boron B typically 1016 1018 cm 3 less highly doped regions generally labeled n p without the pp concentration of holes in p type material pp Na cm 3 Na concentration of acceptor atoms np concentration of electrons in p type material Na np ni2 using mass action law always a lot more p than n in p type material if both Nd and Na present nn Nd Na pp Na Nd ECE 410 Prof F Salem Spring 2009 Example ni2 2 1x1020 Lecture Notes Page 3 8 8 Conduction in Silicon Devices doping provides free charge carriers alters conductivity conductivity in semic w carrier densities n and p q nn pp q electron charge q 1 6x10 19 Coulombs mobility cm2 V sec n 1360 p 480 typical values in bulk Si in n type region nn pn q nnn in p type region pp np q pnp resistivity 1 n p electrons more mobile than holes conductivity of n p Mobility often assumed constant but is a function of Temperature and Doping Concentration Can now calculate the resistance of an n or p region ECE 410 Prof F Salem Spring 2009 Lecture Notes Page 3 9 9 Physical MOSFET Switch nMOS Switch Layers Physical Switching Operation ECE 410 Prof F Salem Spring 2009 Lecture Notes Page 3 10 10 nMOS Layers and Layout Layers of an nMOS tx L channel length W channel width gate oxide separates gate from substrate Side and Top views ECE 410 Prof F Salem Spring 2009 Lecture Notes Page 3 11 11 Physical n pMOS Devices nMOS and pMOS cross section highly doped p region highly doped n region lightly doped n region lightly doped p region Layers substrate n well n p S D gate oxide polysilicon gate S D contact S D metal Can you find all of the diodes pn junctions where conduct in which direction what purpose ECE 410 Prof F Salem Spring 2009 Lecture Notes Page 3 12 12 MOSFET Gate Operation Gate Capacitance gate substrate parallel plate capacitor CG oxA tox F ox 3 9 o o 8 85X10 14 F cm Oxide Capacitance Cox ox tox F cm2 CG Cox AG F channel substrate region under the gate between S and D AG gate area L W cm2 Charge on Gate Q induces charge Q in substrate channel channel charge allows conduction between source and drain ECE 410 Prof F Salem Spring 2009 Lecture Notes Page 3 13 13 Physical Switching in nMOS and pMOS notice nMOS in p substrate pMOS in n substrate nMOS pMOS zero or negative Q on gate no charge in channel positive Q on gate e negative charge in channel conduction path between n S D ECE 410 Prof F Salem Spring 2009 positive Q on gate no charge in channel negative Q on gate VG VS positive charge h in channel conduction path between p S D Lecture Notes Page 3 14 14 Channel Charge and Current Threshold Voltage Vtn Vtp amount of voltage required on the gate to turn tx on gate voltage Vtn p will induce charge in the channel nMOS Channel Charge Qc CG VG Vtn from Q CV because channel holds electrons nMOS Channel Current linear model I Qc tt where tt transit time average time to cross channel tt channel length …
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