Binary AdderHalf-Adder CircuitsFull-AdderFull-Adder CircuitsFull Adder CircuitsFull Adder in CMOSFA Using 2:1 MUXBinary Word AddersRipple Carry AdderAdder/Subtractor using R-C AddersRipple-Carry Adders in CMOSCarry Look-Ahead AdderLogic Circuits for a 4b CLA AdderCLA Carry Generation in Reduced CMOSCLA in Advanced Logic StructuresDynamic Logic –Quick LookManchester Carry Generation ConceptManchester Carry Generation ConceptStatic CMOS Manchester ImplementationStatic CMOS Manchester ImplementationManchester ImplementationManchester ImplementationCLA for Wide Words16b Adder Using 4b CLA BlocksOther Adder ImplementationsFully Differential Full AdderMultiplier BasicsImplementing Multiplier CircuitsSigned Multiplication: Booth Encoding4b x 4b Booth MultiplicationArithmetic/Logic Unit StructureALU Arithmetic ComponentsALU Logic ComponentsExample ALU Organization & FunctionECE 410, Prof. A. Mason Lecture Notes 12.1Binary Adder• Binary Addition– single bit addition– sum of 2 binary numbers can be larger than either number– need a “carry-out” to store the overflow• Half-Adder– 2 inputs (x and y) and 2 outputs (sum and carry)x y x + y (binary sum)0 + 0 = 00 + 1 = 11 + 0 = 11 + 1 = 10 (binary, i.e. 2 in base-10)x y s c0 0 0 00 1 1 01 0 1 01 1 0 1s = x ⊕ yc = x • yXORANDHAxycshalf-adder symbolECE 410, Prof. A. Mason Lecture Notes 12.2Half-Adder Circuits• Simple Logic–using XOR gate• Most Basic Logic– NAND and NOR only circuitsx y s c0 0 0 00 1 1 01 0 1 01 1 0 1s = x ⊕ yc = x • yTake-home Questions:Which of these 3 half-adders will be fastest? slowest? why??Which has fewest transistors? Which transition has the critical delay?ECE 410, Prof. A. Mason Lecture Notes 12.3Full-Adder• When adding more than one bit, must consider the carry of the previous bit– full-adder has a “carry-in” input• Full-Adder Equation• Full-Adder Truth Tableciai+ bici+1sifor every i-th bitcarry-in+ a+ b= carry-out, sumaibicis ci+10 0 0 0 00 1 0 1 01 0 0 1 01 1 0 0 10 0 1 1 00 1 1 0 11 0 1 0 11 1 1 1 1si= ai⊕ bi⊕ cici+1= ai•bi+ ci•(ai⊕ bi)ci+1= ai•bi+ ci•(ai+ bi)if not trying to ‘reuse’ the ai⊕ biterm from sum, can writeFA+aifull-adder symbolbicici+1siECE 410, Prof. A. Mason Lecture Notes 12.4Full-Adder Circuits•XOR-based FA• Other FA Circuits– a few others options are covered in the textbook• HA-based FAFull-Adder Equations: si= ai⊕ bi⊕ ciand ci+1= ai•bi+ ci•(ai⊕ bi)ECE 410, Prof. A. Mason Lecture Notes 12.5Full Adder Circuits• AOI Structure FA– implements following SOP equations– sum delayed from carry• Transmission Gate FA– sum and carry have about the same delayAND OR INVci+1= ai•bi+ ci•(ai+ bi)si= (ai+ bi+ ci) • ci+1+ (ai•bi•ci)ECE 410, Prof. A. Mason Lecture Notes 12.6Full Adder in CMOS• Consider nMOS logic for c_out– two “paths” to ground• Mirror CMOS Full Adder– carry out circuitci+1= ai•bi+ ci•(ai+ bi)– complete circuitai=bi=0ci=0 andai+bi=0ci=1 andai+bi=1ai=bi=1ECE 410, Prof. A. Mason Lecture Notes 12.7FA Using 2:1 MUX• If we re-arrange the FA truth table– can simplify the output (sum, carry) expressions• Implementation– use an XOR to make the decision (a⊕b=0?)– use a 2:1 MUX to select which equation/value of sum and carry to pass to the outputaibicia ⊕ b s ci+10 0 0 0 0 01 1 0 0 0 10 0 1 0 1 01 1 1 0 1 10 1 0 1 1 01 0 0 1 1 00 1 1 1 0 11 0 1 1 0 1If (A ⊕B = 0), SUM=Cin; Cout=A;Else, SUM=Cin_bar; Cout=Cin;ABCinCin_barACinSumCoutA ⊕ BPartial Schematiccan you figure outthe details?ECE 410, Prof. A. Mason Lecture Notes 12.8Binary Word Adders• Adding 2 binary (multi-bit) words– adding 2 n-bit word produces an n-bit sum and a carry–example: 4b addition•Carry Bits– binary adding of n-bits will produce an n+1 carry– can be used as carry-in for next stage or as an overflow flag• Cascading Multi-bit Adders– carry-out from a binary word adder can be passed to next cell to add larger words–example:3 cascaded 4b binary adders for 12b additiona3 a2 a1 a0+ b3 b2 b1 b0c4s3 s2 s1 s04b input a+ 4b input b= carry-out, 4b sumabcarry-outabcarry-outabcarry-incarry-outcarry-inECE 410, Prof. A. Mason Lecture Notes 12.9Ripple Carry Adder• To use single bit full-adders to add multi-bit words– must apply carry-out from each bit addition to next bit addition– essentially like adding 3 multi-bit words•each ciis generated from the i-1 addition–c0will be 0 for addition• kept in equation for generality– symbol for an n-bit adder• Ripple-Carry Adder– passes carry-out of each bit to carry-in of next bit– for n-bit addition, requires n Full-Addersc3 c2 c1 c0a3 a2 a1 a0+ b3 b2 b1 b0c4s3 s2 s1 s0carry-in bits4b input a+ 4b input b= carry-out, 4b sum4b ripple-carry adder using 4 FAsECE 410, Prof. A. Mason Lecture Notes 12.10Adder/Subtractor using R-C Adders• Subtraction using 2’s complements– 2’s complement of X: X2s= X+1• invert and add 1– Subtraction via addition: Y - X = Y + X2s• R-C Adder/Subtactor Cell– control line, add_sub: 0 = add, 1 = subtract– XOR used to pass (add_sub=1) or invert (add_sub=0)– set first carry-in, c0, to 1 will add 1 for 2’s complementbba = add_subECE 410, Prof. A. Mason Lecture Notes 12.11Ripple-Carry Adders in CMOS• Simple to implement and connect for multi-bit addition– but, they are very slow• Worse-case delays in R-C Adders– each bit in the cascade requires carry-out from the previous bit• major speed limitation of R-C Adders– delay depends somewhat on the type of FA implemented– general assumptions• worst delay in an FA is the sum– but carry is more important due to cascade structure• total delay is sum of delays to pass carry to final stage• total delay for n-input R-C addertn= td(a0,b0⇒ c1) + (n-2) td(cin⇒ cout) + td(cin⇒ sn-1)first stage delay: inputs to carry-outmiddle stage (n-2) delay: carry-in to carry-outlast stage delay: carry-in to sumbasic FAcircuitECE 410, Prof. A. Mason Lecture Notes 12.12Carry Look-Ahead Adder• CLA designed to overcome delay issue in R-C Adders– eliminates the ripple (cascading) effect of the carry bits• Algorithm based calculating all
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