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MSU ECE 410 - Cadence Tutorial A: Schematic Entry and Functional Simulation

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Cadence Tutorial A: Schematic Entry and Functional Simulation 1 Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group. Revision Notes: Jun. 2008 Updated for use with Cadence 6.1.2 Waqar A Qureshi & C.Young Jan. 2006 Updated for use with spectre simulator C. Wallace Aug. 2003 update and edit add intro/revision/contents sections standardize document format for all tutorials A. Mason Jan. 2003 modify simulation section M. Parr Aug. 2002 update figures for AMI06 process J. Zhang Jan. 2002 create original tutorial K. Zhang & A. Mason Document Contents Introduction Environment Setup Creating a Design Library Creating a Schematic Cellview Functional Simulation (transient analysis) Introduction This document is one of a three-part tutorial for using CADENCE Custom IC Design Tools for a typical bottom-up digital circuit design flow with the AMIC5N process technology and NCSU design kit. This document, Tutorial A, covers setup of the Cadence environment on a UNIX platform, use of the Virtuoso schematic entry tool, and use of the Virtuoso Analog Design Environment (ADE) analog simulation tool. Tutorial B and C cover other Cadence tools important for custom IC design. Note: Your paths may be different depending on the class or project you are working on. Also note that you can find additional tutorials and notes on the web from courses at other universities. These may be helpful in learning Cadence, but because of differences in the environment setup, you probably will not be able to follow a different tutorial step by step. For more information about Cadence Virtuoso or the ADE tool, see the manuals. Environment Setup Before beginning this tutorial you must setup Cadence to work with your account. The steps for doing this may vary with each class/project, so be sure to follow any class-specific setup steps before proceeding with this tutorial. If you have not already done so, launch Cadence now by going to your working directory and typing virtuoso& at the command prompt. A Command Interpreter Window (CIW) similar to the example below will appear. When all the configuration files have been read, the END OF SITE CUSTOMIZATION message will be displayed indicating the start up was successful. With each new session, Cadence starts a new CDS.log file in your home directory where all the messages that appear in the CIW will be stored. Along with the CIW window, you should also see the Library Manager window that lists the libraries in your working directory. For now the NCSU-Analog-Parts library is the importantCadence Tutorial A: Schematic Entry and Functional Simulation 2 one since it has basic circuit elements like transistors, current sources, voltage sources, ground, resistors, capacitors etc. Command Interpreter Window Library Manager Window In this tutorial, a simplified convention will be used to show the sequence of steps for the pull down menu. For example, File => Exit will indicate that you open the pull down menu for File and then click on Exit. Another example could be Tools => Analog Artist => Simulation, which will indicate that you pull down the Tools menu, then click on the Analog Artist button and finally click on the Simulation button. Note: If at anytime during this tutorial you want to quit Cadence, make sure you save your work by selecting Design => Save and close the design windows by selecting Close from the menu. After you have closed all your working windows, select File => Exit and click Yes in the pop-up confirmation window to end the Cadence session. Cadence File Organization To start a design in Cadence, you must first create a library where you can store your design cells. Every Library is associated with a technology file and it is the technology file that suppliesCadence Tutorial A: Schematic Entry and Functional Simulation 3 the color maps, layer maps, design rules, and extraction parameters required to view, design, simulate and fabricate your circuit. Cadence stores its files in libraries, cells, and cellviews. A library (which actually appears as a directory in UNIX) contains cells (subdirectories), which in turn contain views. Each library contains a catalog of all cells, viewed along with the actual UNIX paths to the data files. Each cell in a library uses the same mask layers, colors, design rules, symbolic devices, and parameter values (i.e. the information contained in the technology file). A cell is the basic design object. It forms an individual building block of a chip or system. It is a logic, rather than a physical, design object. Each cell has one or more views, which are files that store specific data for each cell. A cellview is the virtual data file created to store information in Cadence. A cell may have many cellviews, signifying different ways to represent the same data represented by the cell (for example, a layout, schematic, etc). Example Organization: Library: logic_gates Cell: inv View: schematic View: symbol Cell: nand2 View: schematic View: symbol View: layout View: extracted Library: ripple_carry_adder Cell: 1bit_adder View: schematic Cell: 2bit_adder View: schematic The Custom Design Process For a full custom design (as opposed to a coded/synthesized design using, e.g., Verilog HDL), the design process begins by creating a schematic. The schematic is then simulated to verify operation and optimize performance. A layout of the circuit is generated and checked for design rule violations (DRC). The layout is then extracted and a layout vs. schematic (LVS) comparison is run to ensure the cell layout exactly matches the schematic. Finally the extracted layout is simulated to observe the effect of parasitics that will be present on the fabricated chip. These post layout simulation are closer to reality and will show if your design would work if fabricated. In this tutorial you will create a schematic for a basic digital logic gate, and inverter, and perform some basic simulations on the schematic to verify it is functioning properly. Creating a Design Library STEP 1. • In the Library Manager window, select File => New => Library to open the Create Library window shown below. • Enter a Name for your library. The example shows the library name project1, but since you will probably be using the cells in this library (and adding more to it) choose a name like lab, cmos, or


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MSU ECE 410 - Cadence Tutorial A: Schematic Entry and Functional Simulation

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