ECE 410 Lab 5 Spring 2007 Lab 5: Timing Analysis of Logic Gates Due: Friday February 16th, 2007 Summary: Lab 5 introduces post-layout simulation using extracted parameters from the cell layout and allows students to observe the timing and DC characteristics of some simple CMOS gates. Learning Objectives: 1. Learn how to perform post-layout simulations for timing analysis of CMOS logic gates. 2. Observe the effects of parasitic capacitances on timing characteristics. 3. Learn how to determine the critical path of combinational circuits. Resources: Tutorial C, Guides to Writing Stimulus Files and Automating PWL Source Generation Notes: • For all timing analysis in this lab, use an input voltage pulse rise and fall time of 50ps (rise=0.05n fall=0.05n). This is important in order to obtain consistent results. • Keep a record of all timing measurements obtained for the NAND, NOR, and inverter. You will need them for your report and to complete Lab 6. Procedure: 1. Complete Tutorial C to measure the timing and DC characteristics of the CMOS inverter you have previously designed. The parasitic capacitances from the extracted view will be used along with a load capacitance to simulate the effect of gates attached to the output of the inverter for timing analysis. Accurately measure (a) the propagation delays (high-to-low and low-to-high), (b) rise and fall times, (c) gate switching threshold (midpoint voltage), and (d) output high and low voltages for the inverter. Print/save a copy of a transient analysis waveform and a DC voltage transfer curve for your report. Include the measured results within the Discussion Topics of your report. 2. Using Tutorial C as a guide, measure the timing characteristics for the two-input NAND gate you have previously designed. a. Note: In Lab 2 you should have passed LVS for the NAND (and NOR) with “Allow FET Series Permutations” turned off. This forces the order of series transistors to be the same in both schematic and layout. If you did not do this, you need to or you may get some odd results here. If you are unsure, see the end of Tutorial B for instructions and run LVS again. b. Create a NAND stimulus file (or multiple stimulus files if you prefer) using piecewise linear (PWL) sources to generate two input signals such that ALL possible input transitions that cause an output transition are tested, e.g., 11 → 00, 10 → 11, etc. Notice there are many possible input transitions that do not cause output transitions and therefore do not need to be tested. Be sure to include the 3fF load capacitor in your stimulus file. IMPORTANT: To obtain consistent results for delay measurements, each tested input transition MUST be preceded by setting the inputs to a common value. Here we will use ‘11’. For instance, if you want to test a 10 → 11 transition, you must generate the sequence 11 → 10 → 11. IMPORTANT: For cases where both inputs change, these transitions MUST be setup to occur simultaneously. c. Simulate all output transition cases and measure the propagation delays and rise and fall times for the each output transition of the NAND. Record your results in a table similar to the following example. Lab 5, pg. 1.ECE 410 Lab 5 Spring 2007 Table 2c. Example of data required for Step 2. 00 Æ 11 ?? ?? 11 Æ 00 ?? ?? fall time (ns) rise time (ns) propagation delay, tHL (ns) propagation delay, tLH (ns) d. Notice that propagation delays and rise/fall times will vary depending on the input logic state transition. Observe your results and determine which input transitions caused the worst-case (slowest) delay for each timing characteristic. e. Save or print a sample output waveform that shows markers set to measure the rise and/or fall time. Save or print a sample output waveform that shows markers set to measure the high-to-low and/or low-to-high propagation delay. 3. After simulations of the NAND gate, you should be familiar with writing stimulus files for multi-input gates. To reduce some of the complexity of writing stimulus files, see the Guide to Automating PWL Source Generation. This guide describes how to use a script to simplify generating piecewise linear (PWL) voltage sources in spectre-syntax based on specified input vectors. Identify the input transitions that cause output transitions in a NOR gate and repeat step 2 simulating the two-input CMOS NOR gate you have previously designed. Here you must precede each tested transition with the inputs ‘00’, instead of ‘11’; otherwise, you may receive inconsistent timing results. 4. After you have completed the timing analysis for the NAND and NOR gates, make sure you have the information needed to answer Discussion Topic #2 before continuing. 5. In steps 2 and 3 you were required to set consistent initial values before testing each transition. To analyze why this is necessary, write three separate NAND stimulus files that test the following input bit patterns: (a) 01 → 00 → 11; (b) 10 → 00 → 11; (c) 11 → 00 → 11. You can do these manually or use the automated script. Simulate your NAND gate and measure the high-to-low propagation delay of the 00 → 11 input transition for each of the three input patterns. Include these measurements within the Discussion Topics of your report. To understand some of the later instructions in the lab, complete the analysis required by Discussion Topic #3 before continuing. Note: results may vary depending on your specific layout and which inputs you assign to which transistors. 6. Using Tutorial C as a guide, measure the DC characteristics for the NAND gate. a. Create a stimulus file (or multiple files) that test each possible input transition causing the output to fall from high to low. Refer to previous steps to see which input transitions cause the output to change. For some cases you can set one input high or low with a DC voltage source and do a DC sweep of the second input. For cases where both inputs change value, you can either (a) set both inputs to the same voltage source; or (b) sweep one of the input voltages and short it to the second input through a 0V DC voltage source. b. Measure the gate switching threshold for all possible (output falling) transitions and record their values. Determine which transition has a unique gate switching threshold and include the plot of this case in your report. Your figure caption should identify the logic gate
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