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MSU ECE 410 - Introduction to VLSI Design

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ECE 410, Spring 2009 Introduction to VLSI Design Lecture: MWF, 11:30 12:20, Room 1145 Engineering Bldg (EB) Instructor: Dr. Fathi M. Salem, Office: 2308D EB, Email: [email protected] Office Hrs.: Mon., Wed., Fri. : 2:00-3:00 p.m. TA/Lab Instructor: Sorour Soltani ([email protected]) – TA & Lab TA Hours: TBD LAB Room: 2200 EB* *You may work on your assignments in any available UNIX lab, at any time you wish. The Lab times are when the TA will be available to answer your questions. Course Website: No website. This Semester, we will use the angel management website via (http://www.angel.msu.edu). However, you are encouraged to consult the previous semester’s website at http://www.egr.msu.edu/classes/ece410/mason/, since our material would be closely related to the previous semester’s material. Prerequisite: ECE 230, 302, and 303 Required Text: J. Uyemura, Introduction to VLSI Circuits and Systems, Wiley, 2002. ISBN 0-471-12704-3 Supplementary Text: Weste and Harris, CMOS VLSI Design, 3rd Ed., 2005, ISBN 0-321-14901-7 Baker, Li, Boyce, CMOS Circuit Design, Layout, and Simulation, IEEE Press, 1998. K. Martin, Digital Integrated Circuit Design, 2000, ISBN 0-19-512584-3 Catalog Description: Digital integrated circuit design fundamentals. Design specifications: functionality, performance, reliability, manufacturability, testability, cost. Standards, silicon compilers, foundries. Design layout rules, rule checking. Circuit extraction, simulation, verification. Team-based design. Attendance and Conduct in Class: Students are expected to attend class and be bright and cheerful with lots of questions. It will be hard to do well in this class without attending the lectures. Note that a portion of your grade is based on participation, and excessive absence will lower your grade. It is the student’s responsibility to get notes and handouts for any missed class. Grading: 30% Two Midterm Exams (dates are: Wednesday, March 4th and Friday April 17th) 15% Homework * 5% participation (attendance, quizzes, etc.)* 25% Lab Assignments (Lab 1-7)* 25% Design Project (Labs 8-10, proposal, project demo, project report) * must obtain a passing grade to pass the courseDates for the two midterm exams are above. There is NO final exam, only a final project. Up to ten homework assignments will be due weekly before class on Wednesdays. Approximately 5-10 5-minute quizzes will be given at the beginning of class on random days. Lab Assignments and Lab Project: Lab Assignments using Cadence VLSI design software (available in all Engineering UNIX labs, including rm 3230 EB) will be an integral part of this course. There are no set lab times, but the UNIX lab in EB 3230 has been reserved for ECE410 during several 3-hour blocks. During these times the TA will be available to help answer questions. Details of each assignment will be posted on the course website or via ANGEL. Each registered student already has a UNIX class directory at /classes/ece410/username. Weekly Lab Assignment will have an in-lab check off with the TA that must be completed by 4pm on Friday of the particular Lab week. Reports will include specific deliverables which must be turned in before class on Monday of the following week. There will be 7 “normal” lab assignments plus 3 labs associated with the team-based design project. Each normal lab is worth 20 points, 5 assigned to the check off and 15 to the report. Report grades will be evaluated by your TA and based 60% on the quality of your lab work and 40% on the quality and completeness of your report. The design project will be done in 2-5 person groups. The Lab grades will be assigned according to the following weighting: 10% Proposal 30% Labs 8-10 30% Project Demo 10% Individual 20% Written Report Other Policies: - Cheating in any form will not be tolerated! This includes copying homework, copying circuit design files, cheating on exams, or any other form of unethical behavior. - There is no makeup for missed quizzes. If you have an excusable absence and notify the instructor by email before class begins, missed quizzes will not count against your grade. - Homework can be done in groups but must be turned in individually. Direct copying of homework will result in a zero-point score for all people involved. - Homework must be turned in at the beginning of class on the date it is due (generally Fridays). No late homework will be accepted. - Lab Assignment must be turned-in by 5pm on Wednesday of the week due. Timestamps on CAD files will be checked to ensure work was completed on time. - Makeup exams will only be allowed for excused absences and only when the instructor is informed before the exam. Makeup exams will be oral exams given after the exam


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MSU ECE 410 - Introduction to VLSI Design

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