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MSU ECE 410 - Project Design

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1ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.1ECE410 Design Project-2009 • Deadlines–Draft Proposals: Friday April 3, 2009 (in class) –”Lab 8”:by Friday April 10, 2009 (in lab progress check & proposal discussion)–Proposals: Monday, April 13 (in class) (final Proposal due)–Lab 9: by Friday April 17 (in lab check off, Phase 1)–Lab 10: by Friday April 24 (in lab check off, Phase 2)–Final Demo: by Thursday April 30 (in lab final demonstration)–Report: by Wed, May 5 (by 12pm-noon)• submit reports electronically, in Word, file size less than 3MB•Online Resources–Project Guide: Report and grading guide, etc.–Project Description: Detailed design specifications•Extra Lab Time• –no lectures on Fridays starting April 10 to allow more time for lab• –note: Friday April 17 is Exam level2ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.2Design Project Grading• The combined components of the Design Project are worth 25% of your overall class grade.• Design Project grade will be broken down as:–10% Quality of Proposal–30% “Lab 8-10” Evaluations–25% Final Demo Evaluation–20% Report Quality–15% Individual Effort3ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.3Design Project Grading• The combined components of the Design Project are worth 25% of your overall class grade.• Design Project grade will be broken down as:–10% Quality of Proposal–30% “Lab 8-10”Evaluations–25% Final Demo Evaluation–20% Report Quality–15% Individual Effort74ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.4Design Project Grading5ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.5Design Project Grading6ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.6Design Project Grading7ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.7Your Design Project Design a programmable filter bank: it receives one or more external input signals (x), and output several signal outputs (y). Include “programming” (i.e. download/upload) taps (w) and/or adaptively determine the taps for a given desired output targets (d).•Options:– Follow the (sample) project design for an adaptive filter-bank: use 16 or more input-output filter-bank (i.e., processing array) with (at least) 5-bit storage of the “taps”—vector matrix multiplier. Matrix is 17x16 array (one input for bias!).– Modify to a “transversal” filter-bank: include simple delay lines (e.g. RC delay-line) to process 1d signal with more taps (2n>=256).s(t)s(t-dt)s(t-2dt) s(t-3dt)s(t-ndt)s(t)8ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.8Equations/Formula .111Notation:Signal Input Vector: [ ,..., ]Signal Output Vector:[ ,..., ]Matrix of "weights, parameters, or taps:"[ ], 1,... ; 1,..., .Error Input Vector: [ ,..., ] ;Error OutpTnTmijTmiiixx xyy yWwi nj mee e edy==== ===−1ut Vector:[ ,..., ]Tnδδ δ=For adaptive filteringxyWMultiplier(s)9ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.9Adaptive Filter-Bank Processor .i11y=Wx;or y: :jn jnij j ij ij ij jjjwx y y wx======⇒=∑∑Processor is to compute a vector-matrix multiplication.Ti11=W e;or ::jm jnji j ij ij ji jjjwe weδδδδ======⇒=∑∑Local computation of analog multipliersFor Adaptive Filtering Multiplier cellMultiplier cell10ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.10Cross-bar (array) layout .xjyix1y111ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.11yixjwijMUXcBasic Cell MDACStatic memoryFloating-gateDynamicmemory3 Tap Memory options12ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.12Adaptive Filter-Bank Processor .i11y=Wx;or y: :jn jnij j ij ij ij jjjwx y y wx======⇒=∑∑Processor is to compute a vector-matrix multiplication.Ti11=W e;or ::jm jnji j ij ij ji jjjwe weδδδδ======⇒=∑∑Local computation of analog multipliersFor Adaptive Filtering Multiplier cellMultiplier cell13ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.13yixjDeljeiwijMUXcBasic Cell MDACMemory storageCapacitor2 Multipliers+ a capacitor for tap update14ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.14y1y0ynx1x0xNδ0δNMD ACMu xADC controlwi01D1D1DMD ACw00x0e0w00vb1D1D1DMDACw10x0e1w10vb1D1D1DMDACwn0x0enwn0vb1D1D1DMD ACw01x1e0w01vb1D1D1DMDACw11x1e1w11vb1D1D1DMDACwn1x1enwn1vb1D1D1DMD ACw0nxne0w0nvb1D1D1DMDACw1nxne1w1nvb1D1D1DMDACwnnxnenwnnvbMD ACMuxADC controlMD ACMu xADC controlLearning/ProcessingADC Control Bus MUX Control Busiwine1e0enδ1Basic Cell15ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.15Think in layered design: analog/digital .XXXXXXXXXXXXXXXXXXXXXXXXANALOG /DIGITALINPUTSANALOG/DIGITALOUTPUTS(OPTIONAL)DIGITALINPUTSIGNALSDIGITAL CHIPLEVELCONTROLSIGNALSANALOG NEURALPROCESSINGLAYERDIGITAL STORAGE,PROCESSING AND CONTROLLAYERDIGITAL SUPERVISORY &MULTIPLEXING LAYERRAMXRAMXRAMXRAMXRAMXRAMXCHIPLEVELDECODERCHIPLEVELMUX/DEMUX16ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.16Architectural Design .The chip design is comprised of three stages•High Level (“system” specifications, block definitions)•Component Level (Architectural, simulations)•Layout Level (Cadence LVS, DRC,..)17ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.17User friendly design: think as the end-user .Your chip should operate in (easy) operational modes, e.g.: i. Adapt taps –analogii. (on-chip) Store – analog/digitaliii. Program read/write (taps) – digital iv. Process – analog


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MSU ECE 410 - Project Design

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