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MSU ECE 410 - MICRO-LEARNER

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To: W. Dale Edwards AMD Industrial Assignee to SRC Research Program Manager, Integrated Circuits and Systems Science Semiconductor Research Corporation P.O. Box 12053 Research Triangle Park, NC 27709-2053 Subject: Michigan State University Phase II Copper Design Challenge Report From: Fathi M. Salem (Team Leader) Michigan State University Department of Electrical and Computer Engineering 2120 Engineering Building East Lansing, MI 48824 Email : [email protected] Ph : 517-355-7695 (office) Fax : 517-353-1980Cu Design Challenge Phase II Report Michigan State University (Team # 31) Page : 2 of 100 August 20, 2000 MSU Copper Design Challenge Phase II Report http://www.egr.msu.edu/annweb/cu_contest MICRO-LEARNER A self-programming engine for real-time estimation, prediction, and controlCu Design Challenge Phase II Report Michigan State University (Team # 31) Page : 3 of 100 August 20, 2000 THE TEAM Team for Phase II Dr. Fathi Salem Team Leader [email protected] Rajiv Saini VLSI Layout and Verification [email protected] Khurram Waheed Architecture Design, Circuit Design and Simulation, Layout Verification [email protected] Jian Yu Architectural Design and System-level Simulation [email protected] Design Challenge Phase II Report Michigan State University (Team # 31) Page : 4 of 100 August 20, 2000 Executive Summary The project's goal has been to develop a self-learning computing engine (machine) that supercedes the capabilities of present micro-computing paradigms (micro-processors, micro-controllers, and DSPs) in the application domains of process identification, modeling, prediction, and real-time control. In particular, two domains of prominent applications are (i) biological and medical measurements and stimulation, (ii) vehicle engine misfiring detection and quality quantification of consequent gas exhaust pollution. It is envisioned that incoming data/signals would be processed by this machine in real-time where the outputs may represent estimates of internal states of the process producing the data, predictions about the process's future states, and/or control. In this vision, signals from the (physical or virtual) process to be identified or controlled are continuously supplied to the machine, which in turn performs on-line, instantaneous, learning, adaptation, then processing-- without a traditional code/program! The core of the machine is a novel neurally-inspired scalable (re-configurable) array network for compatibility with VLSI. The machine is inspired from biological neural networks in the retina and the vestibular systems. The machine is endowed with tested "learning" capability for self-configurability realized in hardware to achieve global learning execution times in the micro to milli seconds. It consists of basic building blocks of 4-quadrant multipliers, transconductance amplifiers, and active load resistances, for analog forward network processing and learning modules. Super-imposed on the processing network is a digital memory and control module composed of D-Flip-flops, ADC, and Multiplying D/A Converter (MDAC), and comparators for parameter (weight) storage and analog/digital conversions. The architectural forward and learning networks process in analog continuous-time mode, while the (converged, steady state) weights/parameters can be stored on chip in digital form. The overall architectural design also adopts engineering methods from adaptive networks and optimization principles. The UMC 6 level Cu interconnect process enables dense connectivity and dense die area of this highly interconnected network resulting in a compact powerful engine. Moreover, the special low resistance and low capacitance electric Cu properties permit the design to achieve the high connectivity while still managing precise distributions of resistive and capacitive loads to predict performance and limit signal time-delays along the interconnect. The small feature size and the electric Cu interconnect properties are enablers to the realization of such a proposed machine with dense interconnectivity. The resulting chip design would require no traditional programming or coding. In addition to novel architectural designs, the hardware also performs the computational burden by selectively realizing programmability as on-chip self-learning modules. The resulting chip super-machine would operate on 1.5v power source and would consume less than 1 m Watt. Table of Contents THE TEAM _________________________________________________________________ 3Cu Design Challenge Phase II Report Michigan State University (Team # 31) Page : 5 of 100 August 20, 2000 Executive Summary ___________________________________________________________ 4 Table of Contents _____________________________________________________________ 4 1. Introduction and Overview ___________________________________________________ 8 The WHY: _______________________________________________________________________ 8 The WHAT and HOW:_____________________________________________________________ 8 2. Architectural Level: Neural Architecture _____________________________________ 12 The Synaptic Cell:________________________________________________________________ 12 The Control Cell _________________________________________________________________ 14 3. Simulation and Verification of the Architecture ________________________________ 15 High Level Simulation using Matlab_________________________________________________ 15 HSPICE Simulation ______________________________________________________________ 17 4. Technology setup and Chip Layout __________________________________________ 18 Testing our DRC Rules and New Technology:_________________________________________ 18 Layout of the Chip________________________________________________________________ 19 5. Copper Technology & Interconnect __________________________________________ 21 6. Padframe _______________________________________________________________ 22 7. Chip Testing_____________________________________________________________ 23 Testbench 1: Pure Digital Setup_____________________________________________________ 23 Testbench 2: Mixed Mode Setup ____________________________________________________ 24 8. Applications of our Integrated Circuit ________________________________________ 24 9. Summary and Conclusions


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MSU ECE 410 - MICRO-LEARNER

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