Tutorial PnR: Placement and Routing for a Schematic Created by Zeyong Shan and the AMSaC lab group, Spring 2008 Document Contents Introduction Environment Setup Creating a Verilog Netlist for a Schematic Place and Route with Cadence Encounter Importing the GDSII File into a Virtuoso Library Appendix: ChangeAbstractView Introduction This document will provide students with the methodology for performing place and route with the Cadence Encounter tool. Students will learn to use Cadence Encounter with a standard cell library called OSU_stdcells_ami05 to perform place and route to create the hardware layout from a schematic. Environment Setup The following steps will configure your directory as required by the tutorial: • Log into your account with PuTTY and navigate to your class directory. cd /egr/courses/personal/ece410/<username>/cadence • Copy the map file from the resources directory to your directory. The map file provides the mapping between the place and route tool’s metal layers and polygon layers used in Cadence. cp /egr/courses/personal/ece410/resources/pnr/gds2_icfb.map gds2_icfb.map • Copy the .il file from the resources directory to your directory. cp /egr/courses/personal/ece410/resources/pnr/ChangeAbstractView.il ChangeAbstractView.il This file will be used later in the tutorial and is described in the appendix. • Return to the root of your user directory. Copy the compressed standard cell library. cd /egr/courses/personal/ece410/<username> cp /egr/courses/personal/ece410/resources/pnr/ami05.tar.gz ami05.tar.gz • Decompress the OSU_stdcell_ami05 library with the following command. tar –xzvf ami05.tar.gz • Navigate to your cadence directory again and launch Cadence tools. cd /egr/courses/personal/ece410/<username>/cadence source $SOFT/cadence icfb & • To map the OSU_stdcells_ami05 library into Cadence, go to the Library Manager and select File >> New >> Library. In the Name text box, type OSU_stdcells_ami05. Under Path, enter /egr/courses/personal/ece410/<username>/ami05. In the Technology Cadence Tutorial PnR: Place and Route from Schematic 1Library section, select the Attach to existing tech library option. Select AMI 0.6u C5N (3M, 2P, high-res) from the drop down menu. • Click OK. You should now be able to select the OSU_stdcells_ami05 library in the Library pane and open some cell schematics and layouts. If you cannot, ask the TA for assistance. • The OSU_stdcells_ami05 library is a dependency of the NCSU_TechLib_ami06 library. If you do not have this library mapped to the Front-to-Back Design environment already (i.e., it does not show up in the Library pane), then repeat the process above to add it. The library can be found at the path /egr/courses/personal/ece410/resources. This completes the environment setup. Creating a Verilog Netlist for a Schematic The Verilog netlist is necessary for automated layout (place and route) tools. It contains information about the I/O pins and the connectivity of the entire schematic. Here we take the XOR gate as an example and create its netlist. The cell name of this gate is called XOR. STEP 1: Creating the schematic for XOR gate • First create a new library called PnR. Make sure to attach it to the AMI 0.60u C5N technology library. Fig. 1: Creating the PnR library. • Create a new schematic named XOR under the PnR library. • Instantiate the symbols for INVX1, NAND2X1, and NOR2X1 from the OSU_stdcells_ami05 library into the new/blank schematic. • Build the schematic for an XOR gate shown in Fig. 2 below. Cadence Tutorial PnR: Place and Route from Schematic 2Fig. 2: Schematic for an XOR gate. STEP 2: Initializing Verilog Integration • In the “Virtuoso Schematic Editing Window”, select Tools >> Simulation >> Verilog-XL. • In the “Setup Environment” window that opens (Fig. 3), enter XOR.run1 in the Run Directory text box. All other default values are correct. Click OK. to create the XOR.run1 directory and open the “Virtuoso Schematic Composer Analysis Environment for Verilog-XL Integration” window (Fig. 4). Fig. 3: Setup Environment Fig 4: Environment for Verilog-XL Integration Fig 5: Verilog Netlisting Options STEP 3: Setting the Netlist Options • In the window shown in Fig 4, set the netlisting options by selecting Setup >> Netlist. The Verilog Netlisting Options form opens as shown in Fig 5. • In the …Options window, keep the default settings (shown in Fig 5). Click More>> to access additional options shown in Fig. 6. • In the Fig. 6 options window, o set Global Power Nets to vdd o set Global Ground Nets to gnd o select Generate Pin Map • The Drop Port Range and Preserve Buses options are selected by default and can be left selected for this tutorial. • Click OK to finish setting the Verilog Netlisting Options. Cadence Tutorial PnR: Place and Route from Schematic 3Fig 6: Additional Verilog Netlisting Options STEP 4: Creating the Stimulus File Fig 7: Dialog Box Fig 8: Simulation Options Fig 9: View Netlist Run Files • In the “Virtuoso Schematic Composer Analysis Environment for Verilog-XL Integration” window, select Stimulus >> Verilog. • A dialog box appears as shown in Fig. 7. Click Yes in the dialog box. • In the “Stimulus Options” window that opens, select textfixture.Verilog as the File Name and then click OK. The netlist will be created for the schematic. STEP 5: Creating the Verilog Files To make Verilog files from the netlists: • In the “Virtuoso Schematic Composer Analysis Environment for Verilog-XL Integration” window, select File >> View Netlist Result >> Netlist Run Files …. The “View Netlist Run Files” window (Fig. 9) appears. • Click on the Library Name appearing in the left box (e.g., PnR). The cells in that directory should appear in the Cell Name box. • Click on the cell name (e.g., XOR) and then click View. to open the netlist (Fig. 11). Cadence Tutorial PnR: Place and Route from Schematic 4Fig 11: Netlist for XOR gate • From the netlist window, save the netlist as a Verilog file by selecting File >> Save As…. Save the file with a .v extension (e.g., XOR.v) in any location you wish. • If you have multiple cells, save the netlists for all the cells in a similar way. • Exit “icfb”. Now the Verilog netlist for your design has been created. Next, we will perform placement and routing using Cadence Encounter. Place and Route with Cadence
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