1ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.1Hierarchical Layout of Multiple Cells• “System” of the primitives: Hierarchical “system”– Add instances of (optimized) primitives– Add additional transistor(s)/etc., if necessary • Add substrate/well contacts (plugs)– Add additional polygons where needed• Add metal-1 to make VDD/GND rail continuous• Add n-well to avoid breaks in n-wells that violate rules• Add interconnects and contacts if necessary– Connect signals within cell boundary• If possible, keep internal signals within cell•Ensure cell I/Os to be accessible outside cell– Minimize layout area• Avoid unnecessary gaps between cells– Pass design rule check (DRC)• Do so always and often at every level Continuous power railIn1out2ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.2Signal Buffers3ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.34ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.45ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.5.6ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.6Signal Buffers• Loading and Fan-Out– gate input capacitance•CG= 2CoxWL (1 for pMOS 1 for nMOS)– load capacitance• standard gate designed to drive a load of 3 gates Æ CL= 3CG– output drive capability•I ∝ W, increase W for more output signal drive• increasing W increase CG•Buffers– single stage inverter buffers• isolate internal signals from output load–scaled inverter buffers• add drive strength to a signal• inverters with larger than minimum tx– typically increase by 3x with each stagemin.W/L 3W/L 9W/L 27W/L1x 3x 9x 27xdrive81CGdrive3CGdrive9CGdrive27CGinput cap.CG3CG9CG27CG7ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.7Transmission Gate Multiplexors• Logical Function of a Multiplexor– select one output from multiple inputs– 2:1 MUX logic• CMOS Multiplexors– generally formed using switch logic rather than static• 2:1 MUX using Transmission Gates• 4:1 MUX using 2:1 MUXs8ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.8Pass-gate Multiplexors• 2:1 MUX using pass-gates –nMOS switch circuit• 4:1 MUX using pass-gates• Pass-gate MUX withrail-to-rail output– add full pMOS network• see Figure 11.7 in textbook• Multi-bit MUXs– use parallel single-bit MUXsbuffer foroutput drive9ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.9Binary Decoders• Decoder Basic Function–nbits can be decoded into mvalues•max mis 2n– decoded values are active only one at a time• active high: only selected value is logic 1• active low: only selected value is logic 0•Example: 2/4 (2-to-4) Decoder–2 control bits decoded into 4 values•truth table•equations– active high decoder equations require NOR operationcontrolinputsactive highdecoded outputscontrol inputs select one active outputn select bits decode into 2noutput values10ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.10CMOS Decoder Circuits• 2/4 Active High Decoder• 2/4 Active Low Decoder– implemented with NAND gates• Similar approach for higher-value decodersTruth Table SymbolTruth Table SymbolNAND2 Circuitactive low2/4 decoderNOR2 Circuitactive high2/4 decoder3/8 decoder requires 3-input gates, higher values get complex11ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.11Transmission Gate Decoders•EXAMPLE: 3/8 Active-High Decoder– each output connected to VDD through 3 transmission gates– TG selects set to turn on only one of the 8 possible combinations of the 3-bit select• What do the resistors at output do?• What is the signal value at the unselected outputs?11111011110110011110101011001000d0d1d2d3d4d5d6d7s0s1s212ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.12Magnitude Comparators• Often need to compare the value of 2 n-bit numbers– EQUAL if values are the same– GREATER THAN if a is greater than b– LESS THAN if b is greater than a• Equality: a_EQ_b, can be generated by XNOR operation– a = b iff aXNORb = 1 for each binary digit• example: 4b equality comparator using XNOR– also, a=b if a>b=0 and a<b=0 for ach binary digit• Greater/Less Than, by bit-by-bit comparisona_EQ_b4b GT, LT Logic4b Equality Circuitnote: can get Equalfrom GT, LT circuit13ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.13Combined Comparator Circuits• 8b Magnitude Comparator with Output Enable– generates, EQ (equal), GT (greater than), LT (less than)4-bitcomparatorfrompreviouspagecompares outputs from 4b cells,implements Enable,produces 8b compare results14ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.14Priority Encoders• Priority Encoders generates an encoded result showing –IF a binary number has a logic 1 in any bit– WHERE the most significant logic 1 occurs• Output is an encoded value of the location of the most significant ‘1’• Example: 8b priority encoder• Outputs can be constructed from the truth table– see textbook for illustrations of CMOS logicassign d7highest priority,d0lowestQ2-Q0encode the value ofthe highest priority 1Q3is high if any bit in d is logic 115ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.15Data Latches•Latch Function– store a data value• non-volatile; will not lose value over time– often incorporated in static memory– building block for a master-slave flip flop• Static CMOS Digital Latch– most common structure• cross-coupled inverters, in positive feedback arrangement– circuit forces itself to maintain data value•inverter aoutputs a 1 causing inverter bto output a 0• or, inverter aoutputs a 0 causing inverter bto output a 1BistablecircuitLatches also improve signalnoise immunity; feedbackforces signal to hold valueand filters noise16ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.16D-Latch Logic Circuit• Accessing Latch to Set Value– apply input D to set latched value• NOR D-Latch– uses NOR cells to create latch function• D-Latch with Enable– En selects if output• set by input, D• or from internalfeedback• Different structures used in VLSITransistor-LevelCircuitLogic-LevelCircuit17ECE 410, Prof. A. Mason/Prof. F. Salem Lecture Notes 11.17CMOS VLSI Clocked Latches• Clocked (enable) Latch using TGs– can use TGs to determine• if latch sees D–C = 1 ⇒ Q’ = D’, set data mode• or if positive feedback is applied–C = 0 ⇒ Q’ = Q’, hold data mode• Reducing Transistor Count–Single TG D-Latch• input must
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