Memory BasicsSRAM BasicsSRAM OperationsSRAM Bit Cell Circuit6T Cell DesignSRAM Cell LayoutMulti-Port SRAMMulti-Port SRAM (cont.)SRAM ArraysSRAM Block ArchitectureSRAM Array AddressingSRAM Array AddressingSRAM Array Column CircuitsColumn CircuitryBit line (column) CircuitrySense AmplifiersDRAM BasicsDRAM OperationHold TimeRefresh RateDRAM Read OperationDRAM Read Operation (cont.)DRAM Physical DesignROM BasicsPseudo-nMOS ROMROM ArraysROM Array LayoutProgrammable ROMPROM Storage CellsEPROM ArraysProgramming & Erasing E2PROMsProgrammable Logic ArraysAND-OR PLA ImplementationGate ArraysECE 410, Prof. A. Mason Lecture Notes 13.1Memory Basics•RAM: Random Access Memory– historically defined as memory array with individual bit access– refers to memory with both Read and Write capabilities•ROM: Read Only Memory– no capabilities for “online” memory Write operations– Write typically requires high voltages or erasing by UV light• Volatility of Memory– volatile memory loses data over time or when power is removed•RAM is volatile– non-volatile memory stores date even when power is removed• ROM is non-volatile• Static vs. Dynamic Memory– Static: holds data as long as power is applied (SRAM)– Dynamic: must be refreshed periodically (DRAM)ECE 410, Prof. A. Mason Lecture Notes 13.2SRAM Basics• SRAM = Static Random Access Memory– Static: holds data as long as power is applied– Volatile: can not hold data if power is removed• 3 Operation States–hold–write–read• Basic 6T (6 transistor) SRAM Cell– bistable (cross-coupled) INVs for storage– access transistors MAL & MAR• access to stored data for read and write– word line, WL, controls access•WL = 0, hold operation• WL = 1, read or write operationWLMARMALbit bitECE 410, Prof. A. Mason Lecture Notes 13.3•Hold– word line = 0, access transistors are OFF–data held in latch•Write– word line = 1, access tx are ON– new data (voltage) applied to bit and bit_bar– data in latch overwritten with new value•Read– word line = 1, access tx are ON– bit and bit_bar read by a sense amplifier• Sense Amplifier– basically a simple differential amplifier– comparing the difference between bit and bit_bar• if bit > bit_bar, output is 1• if bit < bit_bar, output is 0• allows output to be set quickly without fully charging/discharging bit lineSRAM OperationsWL=0MARMALbit bitWL=1MARMALbit bitECE 410, Prof. A. Mason Lecture Notes 13.4SRAM Bit Cell Circuit• Two SRAM cells dominate CMOS industry–6T Cell• all CMOS transistors• better noise immunity–4T Cell• replaces pMOS with high resistance (~1GΩ) resistors• slightly smaller than 6T cell• requires an extra high-resistance process layerECE 410, Prof. A. Mason Lecture Notes 13.56T Cell Design• Critical Design Challenge– inverter sizing• to ensure good hold and easy/fast overwrite– use minimum sized transistors to save area• unless more robust design required•Write Operation– both bit and bit_bar applied• inputs to inverters both change• unlike DFF where one INV overrides the other– critical size ratio, βA/βn• see resistor model–want Rn& Rplarger than RA» so voltage will drop across Rn, Rp• typical value, βA/βn=2–so Rn= 2 RA–set by ratio (W/L)Ato (W/L)nResistor ModelWrite 1 OperationECE 410, Prof. A. Mason Lecture Notes 13.6SRAM Cell Layout• Design Challenge– minimum cell size (for high density SRAM array)– with good access to word and bit lines•Example Layout– note WL routed in poly• will create a large RC delayfor large SRAM arrayECE 410, Prof. A. Mason Lecture Notes 13.7Multi-Port SRAM• Allows multiple access to the same SRAM cell simultaneously. – Provide high data bandwidth. • Applications –Register file–Cache–Network switch–ASIC etc.D2D1D1D2Ws1Ws2• A multi-port SRAM cell schematic. Each port has– two access transistors–two bit line– one word selection line. – one address decoder inverter feedback loopbit accessbit_baraccessECE 410, Prof. A. Mason Lecture Notes 13.8Multi-Port SRAM (cont.)• Challenges in multi-ports SRAM.– layout size increases quadratically with # of ports• more word selection lines•more bitlinelines– Æ lower speed and higher power consumption• Multi-port SRAM options for ECE410 Design Project –Two ports• 1 port read and write• 1 port read only–Three ports• 2 ports for read and 1 port for writeECE 410, Prof. A. Mason Lecture Notes 13.9SRAM Arrays• N x n array of 1-bit cells– n = byte width; 8, 16, 32, etc.–N = number of bytes– m = number of address bits•max N = 2m•Array I/O– data, in and out•Dn-1 -D0– address• Am-1 - A0–control• varies with design• WE = write enable (assert low)– WE=1=read, WE=0=write• En = block enable (assert low)– used as chip enable (CE) for an SRAM chipData I/OControlAddressECE 410, Prof. A. Mason Lecture Notes 13.10SRAM Block Architecture• Example: 2-Core design–core width = k•n• n = SRAM word size; 8, 16, etc.• k = multiplier factor, 2,3,4,etc.– shared word-line circuits• horizontal word lines•WL set by row decoder– placed in center of 2 cores– WL in both cores selected at same time• Addressing Operation– address word determines which row is active (which WL =1) via row decoder– row decoder outputs feed row drivers• buffers to drive large WL capacitance•Physical Design– layout scheme matches regular patterning shown in schematic• horizontal and vertical routingExpanded Core ViewBasic SRAMBlock ArchitectureECE 410, Prof. A. Mason Lecture Notes 13.11SRAM Array Addressing• Standard SRAM Addressing Scheme– consider a Nx nSRAM array• N = number of bytes, e.g., 512, 2k• n = byte size, e.g., 8 or 16–maddress bits are divided into xrow bits and ycolumn bits (x+y=m)• address bits are encoded so that 2m= N• array organized with both both vertical and horizontal stacks of bytesRowsColumns1 SRAM byteECE 410, Prof. A. Mason Lecture Notes 13.12SRAM Array Addressing• Address Latch– D-latch with enable and output buffers– outputs both A and A_bar• Address Bits– Row address bits = Word Lines, WL– Column address bits select a subset of bits activated by WL•Column Organization– typically, organized physically by bits, not by bytes– Example, SRAM with 4-bit bytes in 3 columns (y=3)• 3 4-bit bytes in each rowByte 1Byte 2Byte 3D3D2D1D0y0y1y2ColumnAddressAddress Latch(Row) Word Line1 SRAM bit4thbits
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