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MSU ECE 410 - Lab 6

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Lab 6: DFFR Schematic Generation and 8-bit Shift Register Design Due: Thursday March 24, 2009 Summary: In this lab, design techniques for “higher level” digital functional blocks using custom ICdesign tools are introduced and practiced by designing and verifying an 8-bit ShiftRegister. Learning Objectives: 1. Gain understanding of physical design through schematic re-creation. 2. Observe the functionality of a d-type flip flop with reset. 3. Understand design hierarchy at the schematic and physical design level. 4. Observe the functionality of a digital shift register circuit. 5. Learn how to design schematics and layouts for multi-input/output bit structures. Important Notes: • This is a group lab, to be completed by 3-person groups. Team organization anddistribution of workload will be determined by individual groups. This lab is much morecomplex than the prior labs, so plan well, divide and conquer. It is vital that you completesteps 1 and 2 early; most subsequent steps can be done in parallel after completing those. • Each group will submit a single report, and each student will submit an individualanalysis. This is a different format than past reports. See the Guide to Group LabReports. • As with every layout you construct, you must try to minimize the layout area andkeep the cells as compact as possible. Resources: The following documents are available on the class website to provide importantinformation that will assist in completing this assignment. • dffr.tar file located at /egr/courses/personal/ece410/resources/ • Guide to Setting up Group Directories • Lab 7 Supplement • Guide to Multi-Cell Layout • Guide to Power Measurement • Guide to Group Lab Reports Procedure: 1. Complete the procedure described in the Guide to Setting up Group Directories tosetup your group directory. The remainder of this lab is to be preformed once by thegroup working in your group directory. 2. Construct and simulate a D flip flop with reset (DFFR) - Copy the DFFR layout (dffr.tar) from /egr/courses/personal/ece410/resources/into your group design library. At a command prompt, go to where you saved thedffr.tar file and extract it by running the following command: tar -xvf dffr.tarNow you should have the extracted and layout views of the dffr cell in yourgroup library. - Generate the schematic for the provided DFFR cell by mapping the layout to aschematic. The schematic must be made at the transistor level; no gatesymbols can be used. See the Guide to Designing CMOS Flip Flops in Lab 6Supplement for helpful information. o Pass LVS and save your schematic. o Create a symbol for the DFFR cell. o Verify the functionality of the DFFR cell with simulations. Try to showall possible logic cases including asynchronous reset in one simulationplot. Measure the “clock to Q” time for both rising and falling output.Read Discussion Topic 1 before continuing. 3. Construct a 4:1 multiplexer using instances of the 2:1 multiplexer designed in aprevious lab. Create a schematic, a symbol, and a layout that passes DRC and LVS. Youmust maintain a hierarchical design structure by instantiating (not copying) lower levelcells. See the Guide to Multi-cell Layout for additional tips. Verify functionality withsimulations. Read Discussion Topic 2 before continuing. Truth Table for Shift Register 4. Using DFFR and multiplexer cells, construct an 8-bit shift register that can implementthe truth table given here. Refer to class notes and the Lab 6 Supplement document. a. Complete the schematic and verify proper functional operation using schematic-level simulations. You do not need to include these in your report, but you shouldnot begin the next step until you know ALL FUNCTIONS of the shift register areworking correctly. Use a clock of 50MHz. b. Construct the layout of the 8-bit shift register placing all cells in a single row withthe same power supply rails. Pass DRC and LVS. Before extracting, remember torun the command NCSU_parasiticCapIgnoreThreshold=1e-18 in the CommandInterpreter Window to include the parasitic capacitances in the extracted view. c. Complete post-layout simulation for the shift register with CLK at 50MHz.Simulate all functions in the truth table and determine the slowest function. Do afinal simulation of this function to show in your report. Perform a parallel reset of all8 bits at the beginning of your simulation and measure the worst-case delaysS2 S1 S0 Function 0 0 X Parallel Load 0 1 0 Shift Right 0 1 1 Rotate Right 1 0 0 Shift Left 1 0 1 Rotate Left 1 1 X Set ( data output bits go to 1) X X X Reset (when Reset = 1, all data outputs go to 0)(propagation & rise/fall times) for the slowest function of the cell. If necessary, referback to Tutorial C for post layout simulation guidelines. You do not need to reportthe timing for all functions, just the one with the critical path delay. ReadDiscussion Topic 3 before continuing. 5. Review the Guide to Power Measurement and measure the following for extractedviews the DFFR cell and the Shift Register: 1) static power dissipation, 2) dynamicpower dissipation, 3) total average power dissipation. Note the guide has moreinformation that you need to complete this step; the other material is just for yourreference. For the DFFR cell, use a simulation with a 50MHz clock and toggle the Dinput high and low for two cycles at 20MHz (i.e., run simulation for 100n). For the ShiftRegister cell, use your worst- case delay simulation. To avoid unpredictable start-upstates, toggle the reset line at the beginning of your simulations (initiate reset to low andimmediately pull it high). 6. Using the DFFR cell, construct the schematic for an asynchronous counter that cancount to eight (0-7). Perform a schematic-level simulation that verifies counting over 10input cycles. Include the plot in your report and use handwritten annotations to clarifyproper operation. 7. Print the Lab 6 Grading Sheet and check off your lab with a TA by 10pm onThursday. 8. Construct a Group Report of this assignment using the Guide to Writing GroupLab Reports. Include requested data within the appropriate sub-sections of your report,and be sure to include responses to the Discussion Topics


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