Layout of Multiple CellsMulti-Instance CellsHigh-Level LayoutMetal Routing StrategyPower RoutingSignal BuffersTransmission Gate MultiplexorsPass-gate MultiplexorsBinary DecodersCMOS Decoder CircuitsTransmission Gate DecodersMagnitude ComparatorsCombined Comparator CircuitsPriority EncodersData LatchesD-Latch Logic CircuitCMOS VLSI Clocked LatchesFlip Flop BasicsTypes of Flip FlopsJK and T Flip Flops from DFFMaster-Slave D Flip FlopSet/Reset Flip FlopsBuffering in Flip FlopsCharacterizing Flip Flop TimingAnalyzing DFF TimingTransistor Sizing in Flip FlopsLoad Control in Flip FlopsTri-State CircuitsAdvanced Latches and Flip FlopsC2MOS D Flip FlopDiscussion of DFF TimingFlip Flop LayoutFlip Flop Layout IIRegistersShift and Rotate OperationsShift RegisterSwitch Shift/Rotate CircuitsBarrel ShifterAsynchronous CounterSequential CircuitsState Machine ExampleState Machine Example ContinuedSynchronous CounterECE 410, Prof. A. Mason Lecture Notes 11.1Layout of Multiple Cells• Beyond the primitive tier– add instances of primitives– add additional transistors if necessary• add substrate/well contacts (plugs)– add additional polygons where needed• add metal-1 to make VDD/GND rail continuous• add n-well to avoid breaks in n-wells that violate rules• add interconnects and contacts to make signal interconnections– connect signals within cell boundary• if possible, keep internal signal within cell• ensure cell I/Os accessible outside cell– minimize layout area• avoid unnecessary gaps between cells– pass design rule check• ALWAYS, at every cell levelfinal chipprimitivesinternal connectionsin1continuous power railsin2outECE 410, Prof. A. Mason Lecture Notes 11.2Multi-Instance Cells• Cell Placement– pack cells side-by-side• abut cells and align power rails– avoid gaps between cells • unless needed for signal connections• Signal Routing– make internal connections using poly and metal-1, if possible– use jumpers outside rails only when necessary• jump up/down using poly (short trace) or metal-2 (if long trace)– poly for traces close to cell– metal-2 for traces far from cell• leave room for widened power rails• Power Routing– more cells mean more supply current– widen power supply rail for longcascades of cellsinternal connectionsin1continuous power railsin2outwidened power supply railssignal jumperssingle cell cell cascadeXXXXXXXcell Bcell Ccell AECE 410, Prof. A. Mason Lecture Notes 11.3High-Level Layout• Cell Placement– cascade cells with same pitch– stack cascaded cells• Cell Orientation– maintain orientation when stacking• signal jumpers between stacksor–alternate orientation• signal jumpers on top and/or bottom• Power Routing– widen supply rails for long cascades– connect rails outside cell cascades• example followscellcascadeVDDGNDjumpersVDDGNDjumpersVDDGNDGNDVDDjumpersECE 410, Prof. A. Mason Lecture Notes 11.4• General Rules– use lowest level interconnects possible• if process has less than ~3 metal layers– try to route a cell cascade using only poly and metal-1• if process has more than ~3 metals– route cell cascade using metal-1 and metal-2, avoid using poly– alternate directions for each interconnect• e.g., metal1 horizontally, metal2 vertically, metal 3 horizontally, etc.•Example• Note: new process technologies have specially defined metal layers• e.g. metal_5 might be dedicated to VDD routingpoly• within primitives• local interconnects•only if <3 metal layersmetal1• within primitives•power rails• horizontal jumpersmetal2• vertical traces between stacked cascadesMetal Routing StrategyECE 410, Prof. A. Mason Lecture Notes 11.5Power Routing• Power Rails for Combined Cells– join adjacent cells with continuous power rails– keep power rails wide enough for long power traces• more cells Æ more current Æ need traces with lower resistance– power tree concept• power enters chip on one pin• must “branch” across chip• traces should be thicker near pin and narrow into smaller cells• Connecting rails in stacked cell cascadesbranching of power traces across a chip, from thick lines (chip) to thin lines (cell)GND VDDusemanycontacts(vias)jumper areajumper areaVDDGNDVDDGNDVDDGNDcell cascadecellspinchip-levelcell-levelzooming out…VDDGND metal1metal2ECE 410, Prof. A. Mason Lecture Notes 11.6Signal Buffers• Loading and Fan-Out– gate input capacitance•CG= 2CoxWL (1 for pMOS 1 for nMOS)– load capacitance• standard gate designed to drive a load of 3 gates Æ CL= 3CG– output drive capability•I ∝ W, increase W for more output signal drive• increasing W increase CG• Buffers– single stage inverter buffers• isolate internal signals from output load– scaled inverter buffers• add drive strength to a signal• inverters with larger than minimum tx– typically increase by 3x at with each stagemin.W/L 3W/L 9W/L 27W/L1x 3x 9x 27xdrive81CGdrive3CGdrive9CGdrive27CGinput cap.CG3CG9CG27CGECE 410, Prof. A. Mason Lecture Notes 11.7Transmission Gate Multiplexors• Logical Function of a Multiplexor– select one output from multiple inputs– 2:1 MUX logic• CMOS Multiplexors– generally formed using switch logic rather than static• 2:1 MUX using Transmission Gates• 4:1 MUX using 2:1 MUXsECE 410, Prof. A. Mason Lecture Notes 11.8Pass-gate Multiplexors• 2:1 MUX using pass-gates – nMOS switch circuit• 4:1 MUX using pass-gates• Pass-gate MUX withrail-to-rail output– add full pMOS network• see Figure 11.7 in textbook•Multi-bit MUXs– use parallel single-bit MUXsbuffer foroutput driveECE 410, Prof. A. Mason Lecture Notes 11.9Binary Decoders• Decoder Basic Function–nbits can be decoded into mvalues•max mis 2n– decoded values are active only one at a time• active high: only selected value is logic 1• active low: only selected value is logic 0•Example: 2/4 (2-to-4) Decoder– 2 control bits decoded into 4 values•truth table• equations– active high decoder equations require NOR operationcontrolinputsactive highdecoded outputscontrol inputs select one active outputn select bits decode into 2noutputs valuesECE 410, Prof. A. Mason Lecture Notes 11.10CMOS Decoder Circuits• 2/4 Active High Decoder• 2/4 Active Low Decoder– implemented with NAND gates• Similar approach for higher-value decodersTruth Table SymbolTruth Table SymbolNAND2 Circuitactive low2/4 decoderNOR2 Circuitactive high2/4 decoder3/8 decoder requires 3-input
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