1ECE 410, Prof. F. Salem Lecture Notes Page 2.1ECE 410: VLSI DesignCourse Lecture Notes(Uyemura textbook)Professor Fathi SalemMichigan State UniversitySpring 2009Acknowledgement: These are notes of Prof. Mason from Last Semester. We will be updating them, as need arises, this Semester.ECE 410, Prof. F. Salem Lecture Notes Page 2.2Electronics Revolution• Age of electronics– microcontrollers, DSPs, and other VLSI chips are everywhere• Electronics of today and tomorrow– higher performance (speed) circuits– low power circuits for portable applications– more mixed signal emphasis• wireless hardware•high performance signal processing• Sensors, actuators, and microsystemsDigital Camera PDAs CamcorderMP3/CD Player Laptop Cell phoneNintendoGameboyECE 410, Prof. F. Salem Lecture Notes Page 2.3Figure 1.1 (p. 2)The VLSI design funnel.ECE 410, Prof. F. Salem Lecture Notes Page 2.4Figure 1.2 (p.4)General overview of the design heirarchy.2ECE 410, Prof. F. Salem Lecture Notes Page 2.5VLSI Design Flow•VLSI– very large scale integration– lots of transistors integrated on a single chip• Top Down Design– digital mainly–coded design–ECE 411•Bottom Up Design– cell performance–Analog/mixed signal–ECE 410VLSI DesignProcedureSystem SpecificationsLogic SynthesisChip FloorplanningChip-level IntegrationManufacturingFinished VLSI ChipSchematic DesignLVS(layout vs. schematic)Parasitic ExtractionPost-LayoutSimulationDigital CellLibraryMixed-signalAnalog BlocksDRC(design rule check)SimulationPhysical DesignProcess ModelsSPICEProcessCharacterizationProcessDesignProcess Capabilitiesand RequirementsProcessDesign RulesAbstract High-level ModelVHDL, Verilog HDLTopDownDesignBottomUpDesignFunctional SimulationFunctional/Timing/Performance SpecificationsECE 410, Prof. F. Salem Lecture Notes Page 2.6Integrated Circuit Technologies• Why does CMOS dominate?– other technologies• passive circuits• III-V devices• Silicon BJT• CMOS dominates because:– Silicon is cheaper Î preferred over other materials– physics of CMOS is easier to understand–CMOS is easier to implement/fabricate–CMOS provides lower power-delay product–CMOS is lowest power–can get more CMOS transistors/functions in same chip area• BUT! CMOS is not the fastest technology!– BJT and III-V devices are fasterECE 410, Prof. F. Salem Lecture Notes Page 2.7• Physical Structure of a MOSFET Device• Schematic Symbol for 4-terminal MOSFET• Simplified SymbolsMOSFET Physical Viewsource drainSubstrate, bulk, well, or back gategatenMOSpMOScritical dimension = “feature size”ECE 410, Prof. F. Salem Lecture Notes Page 2.8CMOS Technology Trends• Variations over time– # transistors / chip: increasing with time– power / transistor: decreasing with time (constant power density)– device channel length: decreasing with time– power supply voltage: decreasing with timeref: Kuo and Lou, Low-Voltage CMOS VLSI Circuits, Fig. 1.3, p. 3transistors /chippower /transistorchannel lengthsupply voltagelow power/voltage is critical for future ICs3ECE 410, Prof. F. Salem Lecture Notes Page 2.9Moore’s Law• In 1965, Gordon Moore realized there was a striking trend; each new generation of memory chip contained roughly twice as much capacity as its predecessor, and each chip was released within 18-24 monthsof the previous chip. He reasoned, computing power would rise exponentially over relatively brief periods of time.• Moore's observation, now known as Moore's Law, described a trend that has continued and is still remarkably accurate.In 26 yearsthe number of transistors on a chip has increased more than 3,200 times, from 2,300 on the 4004 in 1971 to 7.5 million on the Pentium¨ II processor.10μm1μm0.35μm 45 nm(ref: http://www.intel.com/intel/museum/25anniv/hof/moore.htm)Feature Size180 130 90 60 40 30Feature Size (nm)1999 2001 2004 2008 2011 20141.8 V1.5 V1.2 V0.9 V0.6 V 0.6 VYearPower Supply TendsDigital Core Voltage Projectionsfrom the 2000 ITRS** http://public.itrs.net/Files/2000UpdateFinal/ORTC2000final.pdf2 BillionECE 410, Prof. F. Salem Lecture Notes Page 2.10• MOSFET Device-- 1950+ to 2020• New elements in nano technologies are emerging include: – Memristor: memory resistor- see Dec IEEE Spectrum–Nano-tubes– Molecular devices– Quantum dots–Etc. “Electronics” Building block(s)ECE 410, Prof. F. Salem Lecture Notes Page 2.11VLSI Design Flow•VLSI– very large scale integration– lots of transistors integrated on a single chip• Top Down Design– digital mainly–coded design–ECE 411•Bottom Up Design– cell performance–Analog/mixed signal–ECE 410VLSI DesignProcedureSystem SpecificationsLogic SynthesisChip FloorplanningChip-level IntegrationManufacturingFinished VLSI ChipSchematic DesignLVS(layout vs. schematic)Parasitic ExtractionPost-LayoutSimulationDigital CellLibraryMixed-signalAnalog BlocksDRC(design rule check)SimulationPhysical DesignProcess ModelsSPICEProcessCharacterizationProcessDesignProcess Capabilitiesand RequirementsProcessDesign RulesAbstract High-level ModelVHDL, Verilog HDLTopDownDesignBottomUpDesignFunctional SimulationFunctional/Timing/Performance SpecificationsECE 410, Prof. F. Salem Lecture Notes Page 2.12What is a MOSFET?• Digital integrated circuits rely on transistor switches– most common device for digital and mixed signal: MOSFET• Definitions– MOS = Metal Oxide Semiconductor• physical layers of the device– FET = Field Effect Transistor• What field? What does the field do?• Are other fields important?– CMOS = Complementary MOS• use of both nMOS and pMOS to form a circuit with lowest power consumption.• Primary Features– gate; gate oxide (insulator)– very thin– source and drain–channel–bulk/substratePolyOxideEVgateinsulatorsilicon substratedrain------------channelsourceSemi-conductorNOTE: “Poly” stands for polysilicon in modern MOSFETs4ECE 410, Prof. F. Salem Lecture Notes Page 2.13Fundamental Relations in MOSFET• Electric Fields– fundamental equation• electric field: E = V/d– vertical field through gate oxide• determines charge induced in channel– horizontal field across channel• determines source-to-drain current flow• Capacitance– fundamental equations• capacitor charge: Q = CV• capacitance: C = ε A/d– charge balance on capacitor, Q+ = Q-• charge on gate is balanced by charge in channel• what is the source of channel charge? where does it
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