ECE 410 Homework 4 Spring 2008 REMINDER: You should always try to express answers in appropriate engineering-scale metric units. The common engineering units are factors of 3 (103), such as mm, µm, nm or nF, pF, and fF. Unless otherwise noted in a problem, please convert scientific notation into the most appropriate engineering-scale metric units. This goes for all homework in ECE410. Problem 1 Design a CMOS circuit to implement the following function. )( wzzyxf ⋅+⋅⋅= a) Construct the schematic for the circuit using the minimum number of transistors. b) Sketch the layout for this circuit using a stick diagram using colored pencils/pens/crayons. Show the Euler Path used for your stick diagram on your schematic. The stick diagram should include the active (green), poly (red), metal (blue), and contact (black X) layers and should be implemented between a power (VDD) and ground rail. Problem 2 Identify the fabrication process required to produce the following transistor/circuit features. Choose from the following options: photolithography, diffusion, ion implantation, dielectric deposition, thermal oxidation, chemical etching, or reactive ion etching. a) formation of a native oxide layer at high temperatures b) reproduction of a layout pattern onto a photoresist layer on the surface of a chip c) impurity doping with a maximum concentration at the surface of the wafer d) removal of material with an anisotropic profile e) creation of an insulator layer between metal layers Problem 3 A silicon p-n junction diode is doped with NA = 1016 cm-3 and ND = 5x1014 cm-3. a) Determine the built-in potential of this device b) Assuming Ψ0=0.6V and no reverse bias, calculate the depletion width into the p-type region, xp in μm. c) Assuming Ψ0=0.6V and no reverse bias, calculate the depletion width into the n-type region, xn in μm. d) Calculate the total depletion width as the sum of xn and xp. e) Calculate the total depletion width using the one-sided step junction approximation. What is the percentage error in this approximation? f) If ND = 1x1015 cm-3, would the error from the one-sided step junction approximation become larger or smaller? Problem 4 A 2x2μm area of n+ is diffused into a p-type silicon substrate doped at NA = 1016 cm-3 to form a p-n junction diode that has a built-in potential of 0.75V. a) What is the donor concentration in the n+ region? b) Assuming ND = 1017, what is the total junction capacitance? c) If the equilibrium depletion width is 0.5μm, what is the depletion width if the n+ region is held at 3V relative to the p-type substrate? What is the junction capacitance at this bias voltage if the total junction capacitance at equilibrium is 1fF? Problem 5 a) What is the oxide capacitance, Cox, if the gate oxide of an nMOS transistor is 50nm thick? b) If Cox = 30 nF/cm2, W=1.5μm and L=0.5μm, what is the gate capacitance, Cg? c) If Cg = 1fF and Vtn = 0.5V for the nMOS transistor, what is the value of the channel charge, Qe when VG=1V?. 1d) For pMOS transistor, if Cg = 1fF, Vtp = -0.5V, and VDD=2.5V, what is the value of the channel charge, Qe when VG=1.5V? This is not explicitly covered in class notes, so be careful with voltages and signs; think about what’s going on physically. Problem 6 An nMOS transistor has W=4.5μm and L=0.6μm with process parameters k’n = 110 μA/V2 and Vtn = 0.6V. For each of the cases below, identify the region of operation (cutoff, triode, saturation) and calculate the drain current. Assume VSB = 0V and VDD = 2.2V. a) VGS = 2V, VDS = 1V b) VGS = 2V, VDS = 2V c) VGS = 0.5V, VDS = 2V Problem 7 For each of the bias conditions below, clearly identify the region of operation (cutoff, triode, saturation) and calculate the drain current. Assume the following process parameters and constants: k’n = 100 μA/V2, k’p = 40μA/V2, Vtn=|Vtp|=0.5V, VSB = 0V and VDD = 3V. Ignore channel length modulation and other secondary effects. a) an nMOS device with W=1.5μm and L=0.6μm, VS = 0V, VG = 2V, VD = 1V b) an nMOS device with W=1.5μm and L=0.6μm, VS = 0V, VG = 1.5V, VD = 2.5V c) a pMOS device with W=3μm and L=0.6μm, V S = VDD, VG = 2.75V, VD = 0V d) Use a computer (e.g., Excel, Matlab) to plot the I-V curve (ID vs. VD) for a pMOS device with W=3μm, L=0.6μm, VS = 3V and VG = 2V. On the same plot, repeat for VG = 1V and VG = 0V. Be sure to properly account for transitions between the triode (ohmic) and saturation (active) regions. e) For the transistor in part (a), if VSB increased to 1V but all other parameters remained the same, would the current increase or decrease? Why (what effect is responsible)?
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