Review: CMOS Logic GatesReview: XOR/XNOR and TGsCMOS TechnologyIntegrated Circuit LayersInterconnect ParasiticsMetal Resistance: Measuring ‘squares’Parasitic Line CapacitancesElectrical Properties of SiliconConduction in Semiconductors -ReviewConduction in Silicon DevicesMOSFET Gate OperationPhysical n/pMOS DevicesLower CMOS LayersPhysical Realization of a 4-Terminal MOSFETsCMOS Device DimensionsUpper CMOS LayersCMOS Cross Section ViewInverter LayoutCMOS Layout LayersSeries MOSFET LayoutParallel MOSFET LayoutNAND/NOR LayoutsLayout Cell DefinitionsCell Layout GuidelinesLayout CAD ToolsLayout with Cadence ToolsDesign Rules: IntroDesign Rules: 1Design Rules: 2Design Rules: 3Design Rules: 4Substrate/well ContactsLatch-UpMultiple ContactsCMOS Fabrication ProcessPhotolithographyDoping: DiffusionDiffusionDoping: Ion ImplantationDoping: Ion ImplantationOxidationOxidationCMOS Fabrication SequenceMulti Functional CellsComplex Intra-Cell RoutingExample: Layout of Complex CellMapping Schematics to LayoutStick Diagram method for sketching layoutsStick Diagram NAND & NOREuler “Path”Euler Path ExampleExampleStructured LayoutTransistor OrientationInverter Layout OptionsNAND/NOR Layout AlternativesBuilding Large TransistorsThe Cell ConceptHierarchical DesignCell View and Cell PortsHierarchical Design ConceptsLayout of Large CellsECE 410, Prof. A. Mason Lecture Notes Page 3.1Review: CMOS Logic Gates• NOR Schematicxxyg(x,y) = x yxxyg(x,y) = x + y•NAND Schematic• parallel for OR• series for AND• INV Schematic+Vgs-VoutVinpMOSnMOS+Vsg-= Vin• CMOS inverts functions• CMOS Combinational Logic• use DeMorgan relations to reduce functions • remove all NAND/NOR operations• implement nMOS network• create pMOS by complementing operations• AOI/OAI Structured Logic• XOR/XNOR using structured logicECE 410, Prof. A. Mason Lecture Notes Page 3.2Review: XOR/XNOR and TGs•Exclusive-OR (XOR)–a ⊕ b = a • b + a • b•Exclusive-NOR–a ⊕ b = a • b + a • b• Transmission Gates• MUX Function using TGsbabaXOR/XNOR in AOI Formy = x s, for s=1F = Po • s + P1 • sECE 410, Prof. A. Mason Lecture Notes Page 3.3CMOS Technology• Properties of microelectronic materials– resistance, capacitance, doping of semiconductors• Physical structure of CMOS devices and circuits– pMOS and nMOS devices in a CMOS process– n-well CMOS process, device isolation• Fabrication processes• Physical design (layout)– layout of basic digital gates, masking layers, design rules–LOCOS process– planning complex layouts (Euler Graph and Stick Diagram)Part I: CMOS TechnologyECE 410, Prof. A. Mason Lecture Notes Page 3.4Integrated Circuit Layers• Integrated circuits are a stack of patterned layers– metals, good conduction, used for interconnects– insulators (silicon dioxide), block conduction– semiconductors (silicon), conducts under certain conditions• Stacked layers form 3-dimensional structures• Multi-layer metals– background assumed to besilicon covered by silicon dioxidesiliconsilicondioxidePart I: CMOS TechnologyECE 410, Prof. A. Mason Lecture Notes Page 3.5Interconnect Parasitics• Parasitic = unwanted natural electrical elements• Metal Resistance– metals have a linear resistance and obey Ohm’s law•V = IR– generate parasitic interconnect resistance, Rline•Rline= l= ρl–A = wt– ρ = resistivity, σ = conductivity– defined by sheet resistance• Rs = 1 = ρ , resistance per unit length [ohms, Ω]•Rline= Rsl, Rs determined by process, l & wby designerσAAltwσt twRline = Rswhenl = w Part I: CMOS TechnologyECE 410, Prof. A. Mason Lecture Notes Page 3.6Metal Resistance: Measuring ‘squares’• From top view of layout, can determine how many ‘squares’ of the layer are present– ‘square’ is a unit length equal to the width–Rline= Rs n, where n = l is the number of ‘squares’– Get a unit of resistance, Rs, for each square, n.lwwwn = 8Part I: CMOS TechnologyECE 410, Prof. A. Mason Lecture Notes Page 3.7Parasitic Line Capacitances• Capacitor Basics–Q = CV, C in units of Farads [F]–I = C dV/dt• Parallel plate capacitance–Cline= εoxwl[F], w l = Area– εox= permittivity of oxide• εox= 3.9 εo• εo= 8.85X10-14[F/cm]•RC time constant ofan interconnect line– τ= RlineClinetoxPart I: CMOS TechnologyECE 410, Prof. A. Mason Lecture Notes Page 3.8Electrical Properties of Silicon• Silicon is a semiconductor… does it conduct or insulate?–doping= adding impurities (non-silicon) to Si: will be covered later• doping concentration and temperature determine resistivity• Conduction/Resistance– generally, the Si we see in CMOS is doped• at room temp., doped silicon is a weak conductor = high resistance• Capacitance– doped, room temp. Si is conductive–conduction Æ free charge carriers Æ no electric field Æ no capacitance (within bulk silicon)– exception: if free carries are removed (e.g., depletion layer of a diode) silicon becomes an insulator with capacitancePart I: CMOS TechnologyECE 410, Prof. A. Mason Lecture Notes Page 3.9Conduction in Semiconductors -Review• Intrinsic (undoped) Semiconductors– intrinsic carrier concentration ≡ ni= 1.45x1010cm-3, at room temp.– n = p = ni, in intrinsic (undoped) material•n ≡ number of electrons, p ≡ number of holes– mass-action law, np = ni2applies to undoped and doped material• Extrinsic (doped) Semiconductors– dopants added to modify material/electrical propertiesPBPB++++--group Velementgroup IIIelementionelectronholen-type Donorp-type Acceptorionfreecarrierfreecarrier•n-type (n+), add elements with extra an electron–Nd≡ conc. of donor atoms [cm-3]–nn= Nd, nn≡ conc. of electrons in n-type material–pn= ni2/Nd, using mass-action law, –pn≡ conc. of holes in n-type material–always a lot more n than p in n-type material•p-type = p+, add elements with an extra hole–Na≡ concentration of acceptor atoms [cm-3]–pp= Na, pp≡ conc. of holes in p-type material–np= ni2/Na, using mass-action law, –np≡ conc. of electrons in p-type material–always a lot more p than n in p-type materialPart I: CMOS TechnologyECE 410, Prof. A. Mason Lecture Notes Page 3.10Conduction in Silicon Devices• doping provides free charge carriers, alters conductivity • conductivity in semic. w/ carrier densities n and p– σ = q(μnn + μpp)•q≡ electron charge, q = 1.6x10-19[Coulombs]• μ≡mobility [cm2/V-sec], μn≅ 1360, μp≅ 480
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