CMOS Inverter: DC AnalysisInverter Voltage Transfer CharacteristicsInverter Voltage Transfer CharacteristicsNoise MarginSwitching ThresholdEffect of Transistor Size on VTCExampleCMOS Inverter: Transient AnalysisTransient ResponseFall TimeRise TimePropagation DelaySwitching Speed -ResistanceSwitching Speed -CapacitanceSwitching Speed -Local ModificationCMOS Power ConsumptionMulti-Input Gate Signal TransitionsSeries/Parallel Equivalent CircuitsNAND: DC AnalysisNAND Switching PointNOR: DC AnalysisNAND: Transient AnalysisNOR: Transient AnalysisNAND/NOR PerformanceNAND/NOR Transient SummaryPerformance ConsiderationsTiming in Complex Logic GatesSizing in Complex Logic GatesTiming in Multi-Gate CircuitsPower in Multi-Input Logic GatesTiming Analysis of Transmission GatesPass TransistorECE 410, Prof. A. Mason Lecture Notes 7.1CMOS Inverter: DC Analysis• Analyze DC Characteristics of CMOS Gates by studying an Inverter• DC Analysis– DC value of a signal in static conditions• DC Analysis of CMOS Inverter–Vin, input voltage– Vout, output voltage– single power supply, VDD– Ground reference–find Vout = f(Vin)• Voltage Transfer Characteristic (VTC)– plot of Vout as a function of Vin– vary Vin from 0 to VDD– find Vout at each value of VinECE 410, Prof. A. Mason Lecture Notes 7.2Inverter Voltage Transfer Characteristics• Output High Voltage, VOH– maximum output voltage• occurs when input is low (Vin = 0V)• pMOS is ON, nMOS is OFF• pMOS pulls Vout to VDD–VOH= VDD• Output Low Voltage, VOL– minimum output voltage• occurs when input is high (Vin = VDD)• pMOS is OFF, nMOS is ON• nMOS pulls Vout to Ground–VOL= 0 V•Logic Swing– Max swing of output signal•VL= VOH-VOL•VL= VDDECE 410, Prof. A. Mason Lecture Notes 7.3Inverter Voltage Transfer Characteristics• Gate Voltage, f(Vin)–VGSn=Vin, VSGp=VDD-Vin• Transition Region (between VOHand VOL)–Vinlow•Vin< Vtn–Mnin Cutoff, OFF– Mp in Triode, Vout pulled to VDD•Vin> Vtn< ~Vout– Mn in Saturation, strong current– Mp in Triode, VSG& current reducing– Vout decreases via current through Mn– Vin = Vout (mid point) ≈ ½VDD– Mn and Mp both in Saturation– maximum current at Vin = Vout–Vinhigh• Vin > ~Vout, Vin < VDD - |Vtp|– Mn in Triode, Mp in Saturation• Vin > VDD - |Vtp|–Mnin Triode, Mp in Cutoff+VGSn-+VSGp-Vin < VILinput logic LOWVin > VIHinput logic HIGH•Drain Voltage, f(Vout)–VDSn=Vout, VSDp=VDD-VoutECE 410, Prof. A. Mason Lecture Notes 7.4Noise Margin•Input Low Voltage, VIL– Vin such that Vin < VIL= logic 0– point ‘a’ on the plot•where slope,• Input High Voltage, VIH– Vin such that Vin > VIH= logic 1– point ‘b’ on the plot•where slope =-1• Voltage Noise Margins– measure of how stable inputs are with respect to signal interference–VNMH= VOH-VIH= VDD - VIH–VNML= VIL-VOL= VIL– desire large VNMHand VNMLfor best noise immunity1−=∂∂VoutVinECE 410, Prof. A. Mason Lecture Notes 7.5Switching Threshold• Switching threshold = point on VTC where Vout = Vin– also called midpoint voltage, VM– here, Vin = Vout = VM• Calculating VM–at VM, both nMOS and pMOS in Saturation– in an inverter, IDn= IDp, always!– solve equation for VM– express in terms of VM– solve for VMDptpSGpptnGSnntnGSnOXnDnIVVVVVVLWCI =−=−=−=222)(2)(2)(2ββμ22)(2)(2tpMDDptnMnVVVVV −−=−ββ⇒tpMDDtnMpnVVVVV −−=− )(ββpnpntntpMVVVDDVββββ++−=1ECE 410, Prof. A. Mason Lecture Notes 7.6Effect of Transistor Size on VTC•Recall• If nMOS and pMOS are same size–(W/L)n = (W/L)p–Coxn= Coxp(always)•If• Effect on switching threshold–if βn≈βpand Vtn = |Vtp|, VM= VDD/2, exactly in the middle• Effect on noise margin–if βn≈βp, VIHand VILboth close to VMand noise margin is goodLWknn'=βppnnpnLWkLWk⎟⎠⎞⎜⎝⎛⎟⎠⎞⎜⎝⎛=''ββpnpntntpMVVVDDVββββ++−=132orLWCLWCpnpoxppnoxnnpn≅=⎟⎠⎞⎜⎝⎛⎟⎠⎞⎜⎝⎛=μμμμββ1, =⎟⎠⎞⎜⎝⎛⎟⎠⎞⎜⎝⎛=pnnppnthenLWLWββμμsince L normally min. size for all tx,can get betas equal by making Wp larger than WnECE 410, Prof. A. Mason Lecture Notes 7.7Example•Given– k’n = 140uA/V2, Vtn = 0.7V, VDD = 3V– k’p = 60uA/V2, Vtp = -0.7V•Find– a) tx size ratio so that VM= 1.5V–b) VMif tx are same sizetransition pushed loweras beta ratio increasesECE 410, Prof. A. Mason Lecture Notes 7.8CMOS Inverter: Transient Analysis• Analyze Transient Characteristics of CMOS Gates by studying an Inverter• Transient Analysis– signal value as a function of time• Transient Analysis of CMOS Inverter– Vin(t), input voltage, function of time– Vout(t), output voltage, function of time– VDD and Ground, DC (not function of time)– find Vout(t) = f(Vin(t))• Transient Parameters–output signal rise and fall time– propagation delayECE 410, Prof. A. Mason Lecture Notes 7.9Transient Response• Response to step change in input– delays in output due to parasitic R & C•Inverter RC Model– Resistances–Rn= 1/[βn(VDD-Vtn)]–Rp= 1/[βn(VDD-|Vtp|)]–Output Cap. (only output is important)•CDn(nMOS drain capacitance)–CDn= ½ Cox WnL + CjADnbot+ CjswPDnsw•CDp(pMOS drain capacitance)–CDp= ½ Cox WpL + CjADpbot+ CjswPDpsw• Load capacitance, due to gates attached at the output–CL= 3 Cin = 3 (CGn+ CGp), 3 is a “typical” load• Total Output Capacitance–Cout= CDn+ CDp+ CL+Vout-CLterm “fan-out” describes# gates attached at outputECE 410, Prof. A. Mason Lecture Notes 7.10Fall Time• Fall Time, tf– time for output to fall from ‘1’ to ‘0’–derivation:• initial condition, Vout(0) = VDD• solution– definition•tfis time to fall from90% value [V1,tx] to 10% value [V0,ty]•tf= 2.2 τnnoutoutoutRVtVCi =∂∂−=ntDDeVtVoutτ−=)(τn= RnCouttime constant⎟⎠⎞⎜⎝⎛=VoutVtDDnlnτ⎥⎦⎤⎢⎣⎡⎟⎟⎠⎞⎜⎜⎝⎛−⎟⎟⎠⎞⎜⎜⎝⎛=DDDDDDDDnVVVVt9.0ln1.0lnτECE 410, Prof. A. Mason Lecture Notes 7.11Rise Time•Rise Time, tr– time for output to rise from ‘0’ to ‘1’–derivation:• initial condition, Vout(0) = 0V• solution– definition•tfis time to rise from10% value [V0,tu] to 90% value [V1,tv]•tr= 2.2 τp• Maximum Signal Frequency–fmax= 1/(tr+ tf)• faster than this and the output can’t settleτp= RpCouttime constantpoutDDoutoutRVVtVCi−=∂∂=⎥⎦⎤⎢⎣⎡−=−ptDDeVtVoutτ1)(ECE 410, Prof. A. Mason Lecture Notes 7.12Propagation Delay• Propagation Delay,
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