1ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates Lecture Notes Page 5.1CMOS Process Flow• See supplementary power point file for animated CMOS process flow (see class ece410 website). The file should be viewed as a slide show--it is not designed for printing.2ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates Lecture Notes Page 5.2Layout CAD Tools• Layout Editor– draw multi-vertices polygons which represent physical design layers– Manhattan geometries, only 90º angles• Manhattan routing: run each interconnect layer perpendicular to each other•Design Rules Check (DRC)– checks rules for each layer (size, separation, overlap)–must pass DRC or will fail in fabrication• Parameter Extraction– create netlist of devices (tx, R, C) and connections– extract parasitic Rs and Cs, lump values at each line (R) / node (C)• Layout Vs. Schematic (LVS)– compare layout to schematic– check devices, connections, power routing• can verify device sizes also– ensures layout matches schematic exactly–passing LVS is final step in layout3ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates Lecture Notes Page 5.3CMOS Layout Layers• Mask layers for 1 poly, 2 metal, n-well CMOS process– Background: p-substrate–nWell–Active–Poly–pSelect–nSelect–Active Contact–Poly Contact–Metal1–Via–Metal2–Overglass4ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates Lecture Notes Page 5.4Design Rules: Intro• Why have Design Rules– fabrication process has minimum/maximum feature sizes that can be produced for each layer– alignment between layers requires adequate separation (if layers unconnected)or overlap (if layers connected)– proper device operation requires adequate separation•“Lambda”Design Rules– lambda, λ, = 1/2 minimum feature size, e.g., 0. 6μmprocess -> λ =0.3μm– can define design rules in terms of lambdas• allows for “scalable” design using same rules•Basic Rules– minimum layer size/width– minimum layer separation– minimum layer overlap5ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates Lecture Notes Page 5.5Design Rules: 1•n-well– required everywhere pMOS is needed–rules• minimum width• minimum separation to self• minimum separation to nMOS Active• minimum overlap of pMOS Active•Active– required everywhere a transistor is needed– any non-Active region is FOX–rules• minimum width• minimum separation to other Active3λMOSIS SCMOS rules; λ =0.3μm for AMI C5N10λ6λ3λ5λ6ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates Lecture Notes Page 5.6Design Rules: 2• n/p Select– defines regions to be doped n+ and p+–txS/D = Active AND Select NOT Poly– tx gate = Active AND Select AND Poly–rules• minimum overlap of Active– same for pMOS and nMOS• several more complex rules available•Poly– high resistance conductor (can be used for short routing)– primarily used for tx gates–rules• minimum size• minimum space to self• minimum overlap of gate• minimum space to Active2λ2λ2λ1λ2λgate =Active-Poly-Select7ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates Lecture Notes Page 5.7Design Rules: 3•Contacts– Contacts to Metal1, from Active or Poly• use same layer and rules for both–must be SQUARE and MINIMUM SIZED–rules•exact size• minimum overlap by Active/Poly• minimum space to Contact• minimum space to gate•Metal1– low resistance conductor used for routing–rules• minimum size• minimum space to self• minimum overlap of Contact2λ1.5λ2λ2λ2λ3λ1λ5λnote: due to contact sizeand overlap rules, min.active size at contact willbe 2+1.5+1.5=5λ4λif wide2λ8ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates Lecture Notes Page 5.8Design Rules: 4•Vias– Connects Metal1 to Metal2–must be SQUARE and MINIMUM SIZED–rules•exact size•space to self• minimum overlap by Metal1/Metal2• minimum space to Contact• minimum space to Poly/Active edge•Metal2– low resistance conductor used for routing–rules• minimum size• minimum space to self• minimum overlap of Via3λ1λsee MOSIS sitefor illustrationshttp://www.mosis.org3λ2λ3λ1λ2λ2λ6λif wide9ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates Lecture Notes Page 5.9Physical Realization of a MOSFET•nMOS Layout– gate is intersection of Active, Poly, and nSelect– S/D formed by Active with Contact to Metal1– bulk connection formed by p+ tap to substrate•pMOS Layout– gate is intersection of Active, Poly, and pSelect– S/D formed by Active with Contact to Metal1– bulk connection formed by n+ tap to nWell•Effective Gate Size– S/D will diffuse under the gate• effective channel length is less than drawn•Leff= L(drawn) -2LD– FOX will undercut active region• effective channel width is less than drawn•Weff= W(drawn) -ΔW–LDand Δ W defined by fab. process– generally taken care of by SPICEGateDSBulkGroundGateDSBulkVDDL(drawn)LeffLD10ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates Lecture Notes Page 5.10Substrate/well Contacts• Substrate and nWells must be connected to the power supply within each cell– use many connections to reduce resistance– generally place • ~ 1 substrate contact per nMOS tx• ~ 1 nWell contact per pMOS tx– this connection is called a tap, or plug– often done on top of VDD/Ground rails– need p+ plug to Ground at substrate– need n+ plug to VDD in nWelln+plugto VDDp+plugto Ground11ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates Lecture Notes Page 5.11Latch-Up• Latch-up is a very real, very important factor in circuit design that must be accounted for• Due to (relatively) large current in substrate or n-well– create voltage drops across the resistive substrate/well• most common during large power/ground current spikes– turns on parasitic BJT devices, effectively shorting power & ground• often results in device failure with fused-open wire bonds or interconnects– hot carrier effects can also result in latch-up• latch-up very important for short channel devices•Avoid latch-upby– including as many substrate/well contacts as possible• rule of thumb: one “plug” each time a tx connects to the power rail– limiting the maximum supply current on the chip12ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates Lecture Notes Page 5.12Multiple Contacts• Each contact has a characteristic resistance, Rc• Contact
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