NAME: Exam 1 ECE 410 Fall 2002 During this exam you are allowed to use a calculator and the equations sheet provided. You are not allowed to speak to or exchange books, papers, calculators, etc. with other students. Total Points: 100 Time: 60 minutes (11:30pm – 12:30pm) • Write your name at the top of the exam and your initials at the top of each sheet. • Sign the honor pledge at the end of the exam. • Show all of your work. Try to use only the pages provided (write on back if necessary) • Give units in your answers. • Note the point value of each question and try to at least attempt each problem. Partial credit will be given for all problems involving calculations. True or False: For each of the following statements, circle T if it is true and F if it is false. 2 pts. each. T F 1. Two series switches controlled by A and B form the function A OR B. T F 2. The maximum output voltage from a pMOS transistor with its Source connected to VDD will be VDD – |Vtp|. T F 3. In a CMOS inverter, when the input is logic-high, the pMOS device is ON and the nMOS device is OFF. T F 4. A CMOS NAND gate contains two parallel pMOS transistors. T F 5. In a CMOS gate, if the inputs to nMOS are A and B, the inputs to pMOS will be A’ and B’. T F 6. A transmission gate is formed by placing an nMOS transistor in series with a pMOS transistor and connecting both inputs to a select/control signal. T F 7. In the fabrication process of diffusion, the dopant concentration is greatest at the exposed (top) surface of the substrate wafer. T F 8. Adding multiple contacts between layout layers (e.g., metal and poly) increases the resistance. T F 9. The width of a pn junction depletion layer depends highly on the dopant concentration in the lightly doped side of the junction. T F 10. Propagation delay describes the time it takes for the input to rise from a low value to a high value.ECE 410, Exam 1 Fall 2002 2 Multiple Choice: In the box beside each question, write the letter for the ONE answer that best fits the question/statement. 3 pts. each. 11. Which of the following is a reason why silicon CMOS circuits dominates the IC industry? A) can get more CMOS gates in same chip area B) CMOS gates are faster than any other logic structures C) silicon is an expensive material D) CMOS physics is complex to understand 12. Which of the following is a layout layer in an n-well CMOS process? A) n-type substrate B) contact C) p-well D) transistor gate 13. Which of the following CMOS logic circuits will contain parallel nMOS transistors? A) NOR B) Transmission Gate C) NAND D) Inverter 14. Which of the following CMOS gates can be implemented using AOI structured logic? A) Inverter B) XOR C) Transmission Gate D) none of the above 15. Which of the following would have the highest mobility, µ. A) electrons deep in the substrate B) electrons near the surface of the substrate C) holes deep in the substrate D) holes near the surface of the substrate 16. Which of the following layers is NOT needed to layout an nMOS transistor? A) active B) via C) poly D) n-select 17. A nMOS transistor will have a collection of positive charges under the gate oxide during: A) accumulation B) depletion C) inversion D) all of the above 18. Which of the following circuits would utilize an nMOS shared junction without contact? A) INV B) NOR C) NAND D) NOR3 19. Which of the following is a disadvantage of using high-level metals within primitive cells? A) higher transistor packing density B) more metal layers needed for complete chip layout C) less chip area required for routing D) less resistance between cells 20. Which of the following causes the drain current to increase with VDS in the saturation region? A) channel length modulation B) inversion charge in the channel C) the body effect D) hole mobilityECE 410, Exam 1 Fall 2002 3 Calculation: Solve the following problems in the space provided and on the backs of these pages if necessary. You must show ALL major step on these test pages. Unless otherwise noted, for all problems assume minimum feature size = 2λλλλ = 0.6µµµµm, and VDD = 3V. 21. Conductivity & RC Model: 15 points Consider the nMOS transistor shown to the right which has a substrate doping of NA = 1x1016cm-3. a) What is the electron concentration in the channel at equilibrium (no bias voltages)? ANSWER: np = cm-3 b) What is the hole concentration in the channel at equilibrium? ANSWER: pp = cm-3 c) If the equilibrium channel conductivity is 0.04 [ΩΩΩΩ-cm]-1 what is the equilibrium resistance of the channel (from source to drain)? Include lateral diffusion under the gate in your calculation. ANSWER: R = [kΩ] d) What is the drain capacitance of this device under zero-bias pn junction conditions assuming Cox = 3fF/µµµµm2, Cj = 1fF/µµµµm2, and Cjsw = 0.2fF/µµµµm? Include effects of lateral diffusion. ANSWER: CD = [fF] e) What is the RC time constant, τn, of this device at the drain node if the source is connected to ground and the resistance of the channel during inversion is Rn = 100ΩΩΩΩ? Assume CD = CS = 20fF. ANSWER: τn = [psec] PolyActive0. 1 mµ0. 8 mµ0.2 mµ1. 5 mµ1.5 mµChannelECE 410, Exam 1 Fall 2002 4 22. MOSFET Voltages: 10 points Find the requested voltages in the following circuit by applying the rules for cases where 2 terminal voltages are known. Assume Vtn = |Vtp| = 0.5V for all transistors. a) For the circuit on the right, what is the voltage at the output of the inverter, Vx? ANSWER: Vx = V b) What is Vo? ANSWER: Vo = V 23. MOSFET Currents: 13 points a) For each of the following bias voltages, specify the region of operation (cutoff, triode, or saturation). Assume Vtn = |Vtp| = 0.5V. i) nMOS with VD = 2V, VG = 1V, and VS = 0V. REGION: ii) nMOS with VD = 2V, VG = 0V, and VS = 1V. REGION: iii) pMOS with VD = 2V, VG = 1V, and VS = 3V. REGION: iv) pMOS with VD = 0V, VG = 1.5V, and VS = 3V. REGION: b) For case (i) above, calculate the nMOS drain current neglecting body effect and channel length modulation and do not adjust for effective channel length. Assume W=1.8µµµµm, L=0.6µµµµm and µµµµ Cox = 50µµµµA/V. ANSWER: ID = µA VD D = 3VVD DVDDVi=0V VoVxECE 410, Exam 1 Fall 2002
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