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MSU ECE 410 - AdvancedTopologiesandTechnology

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CMOS Logic FamiliesnMOS InverterPseudo-nMOSPseudo nMOS DC OperationPseudo nMOS Transient AnalysisDifferential LogicDifferential LogicDynamic LogicDynamic LogicCharge Redistribution in Dynamic LogicDomino LogicPass Transistor (PT) LogicVTC of PT AND GatenMOS Only PT Driving an InverterVoltage Swing of PT Driving an InverterTG Full AdderBasic CMOS Isolation StructuresLOCOSProblems with LOCOSShallow Trench Isolation (STI)Lightly-Doped Drain (LDD)Silicon On Insulator (SOI)BiCMOSScaling OptionsLow Voltage IssuesShort ChannelsShort Channel EffectsVelocity SaturationHot Carrier EffectsHot Carrier Effects IILeakage CurrentsLatch-UpSubthreshold OperationSubthreshold OperationECE 410, Prof. A. Mason Advanced Digital.1CMOS Logic Families• Many “families” of logic exist beyond Static CMOS• Comparison of logic families for a 2-input multiplexer• Briefly overview–pseudo-nMOS– differential (CVSL)– dynamic/domino– complementary pass-gateECE 410, Prof. A. Mason Advanced Digital.2nMOS Inverter•Logic Inverter•nMOS Inverter– assume a resistive load to VDD– nMOS switches pull output low based on inputs• Active loads– use pMOS transistor in place of resistor– resistance varies with Gate connection•Ground Æ always on• Drain=Output Æ turns off when Vout > VDD-Vtp–VSG= VSDso always in saturation• Vbias Æ can turn Vbias for needed switching characteristicsnMOS Inverter (a) nMOS is off,(b) nMOS is onx yxy0110= xVbiasECE 410, Prof. A. Mason Advanced Digital.3Pseudo-nMOSgeneric pseudo-nMOS logic gatepseudo-nMOSinverterpseudo-nMOS NAND and NOR• full nMOS logic array• replace pMOS array with single pull up transistor• Ratioed Logic– requires proper tx size ratios•Advantages– less load capacitance on input signals• faster switching– fewer transistors• higher circuit density•Disadvantage– pull up is always on• significant static power dissipation–VOL> 0ECE 410, Prof. A. Mason Advanced Digital.4Pseudo nMOS DC Operation• Output High Voltage, VOH(Maximum output)– occurs when input is low (Vin = 0V), nMOS is OFF– pMOS has very small VSDÆ triode operation– pMOS pulls Vout to VDD–VOH= VDD• Output Low Voltage, VOL (Minimum output)– occurs when input is high (Vin = VDD)– both nMOS and pMOS are ON• nMOS is “on stronger”; pulls Vout low– as Vout goes low, nMOS enters triode• continues to sink current from pMOS load–VOL> 0 V (active load always pulling)• Logic Swing (max output swing)–VL= VOH-VOL< VDDpseudo nMOSinverter VTCVOH= VDDVOL> GroundECE 410, Prof. A. Mason Advanced Digital.5Pseudo nMOS Transient Analysis• Rise and Fall Times– harder to analyze for pseudo nMOS– due to “always on” active loadslow rise timefaster fall timebut does not fall to 0 voltsECE 410, Prof. A. Mason Advanced Digital.6Differential Logic• Cascode Voltage Switch Logic (CVSL)– aka, Differential Logic• Performance advantage of ratioedcircuits without the extra power• Requires complementary inputs– produces complementary outputs•Operation– two nMOS arrays•one for f, one for f–cross-coupled load pMOS– one path is always active• since either f or f is always true– other path is turned off • no static powergeneric differential logic gatedifferential AND/NAND gate(logic arrays turns off one load)ECE 410, Prof. A. Mason Advanced Digital.7Differential Logic• Advantages of CVSL– low load capacitance on inputs– no static power consumption– automatic complementary functions•Disadvantages– requires complementary inputs– more transistors• for single function• Very useful in some circuit blocks where complementary signals are generally needed– interesting implementation in addersdifferential 4-input XOR/XNORECE 410, Prof. A. Mason Advanced Digital.8Dynamic Logic• Advantages of ratioed logic without power consumption of pseudo-nMOS or excess tx of differential• Dynamic operation: output not always valid• Precharge stage– clock-gated pull-up precharges output high– logic array disabled• Evaluation stage–prechargepull-up disabled– logic array enabled & if true, discharges outputgeneric dynamic logic gateECE 410, Prof. A. Mason Advanced Digital.9Dynamic Logic• Example: Footed dynamic NAND3• Footed vs. Unfooted– foot tx ensures nMOS array disabled during prechargeunfootedfootedECE 410, Prof. A. Mason Advanced Digital.10Charge Redistribution in Dynamic Logic• Major potential problem– during evaluation, precharge charge is distributed over parasitic capacitances within the nMOS array• causes output to decrease (same charge over larger C Æ less V)– if the function is not true, output should be HIGH but could be much less than VDDcharge distribution over nMOSparasitics during evaluation• One possible solution– “keeper” transistor• injects charge during evaluation if output should be HIGH• keeps output at VDD– keeper controlled by output_bar• on when output is highECE 410, Prof. A. Mason Advanced Digital.11Domino Logic• Dynamic logic can only drivean output LOW– output HIGH is precharged only with limited drive• Domino logic adds and inverter buffer at output• Cascading domino logic– must alter precharge/eval cycles– clock each stage on oppositeclock phasegeneric domino logic gateNP dynamic logicNO RAce (NORA) domino logicECE 410, Prof. A. Mason Advanced Digital.12Pass Transistor (PT) LogicABFB0A0BB= A • BF= A • B Gate is static – a low-impedance path exists to both supply rails under all circumstances N transistors instead of 2N No static power consumption Ratioless Bidirectional (versus undirectional)ECE 410, Prof. A. Mason Advanced Digital.13VTC of PT AND GateA0BBF= A•B1.2/0.61.2/0.61.2/0.62.4/0.6012012B=VDD, A=0→VDDA=VDD, B=0→VDDA=B=0→VDDVout, VVin, Vz Pure PT logic is not regenerative - the signal gradually degrades after passing through a number of PTs (can fix with static CMOS inverter insertion)ECE 410, Prof. A. Mason Advanced Digital.14nMOS Only PT Driving an Inverter•Vxdoes not pull up to VDD, but VDD–VTnIn = VDDA = VDDVx= VDD-VTnM1M2BSD• Threshold voltage drop causes static power consumption (M2may be weakly conducting forming a path from VDDto GND)•Notice VTnincreases of pass transistor due to body effect(VSB)VGSECE 410, Prof. A. Mason Advanced Digital.15Voltage Swing of PT Driving an Inverter•Body effect–large VSBat x - when pulling high (B is tied to GND and S charged up close to VDD)• So the voltage


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