Tutorial PnR: Place and Route Created for the MSU VLSI program by Pete Semig, Fall 2004 Updated: S05, S06 Document Contents Introduction Environment Setup Synthesis with Synopsys Design Vision Place & Route with Cadence Silicon Ensemble Importing the GDSII File into a Virtuoso Library Simulating from an Extracted Netlist Introduction This document will provide students with the methodology for performing place and route (P&R) with the Synopsys and Cadence tools. We will use a standard cell library created by Illinois Institute of Technology that is compatible with the MOSIS AMI C5N process. Students will learn how to perform synthesis with Synopsys Design Vision (aka Design Compiler) and P&R with Cadence’s Silicon Ensemble. Environment Setup The setup for this tutorial is extremely important. Please execute the following series of commands very carefully: 1. Open a terminal window and go to your class directory. For example, cd /egr/courses/personal/ece410/<username>/ 2. Create two folders called synopsys and se, and then go to the synopsys directory. mkdir synopsys mkdir se cd synopsys 3. Copy some files you will need for this tutorial to your directory with the following command. cp /egr/courses/personal/ece410/resources/pnr/*.* . Note: you must include the last ‘.’, with a space between the last ‘*’ and the last ‘.’. This will copy pnr_setup.tar and adder8.v to your /synopsys directory. 4. Expand the .tar file tar xvf pnr_setup.tar This will create directories WORK, db, lef, map, muxcase and v under /synopsys. In these six directories you will find all the files needed to perform place & route. From here on, references to these directories will only include the directory name, not the absolute path. For example, if you are requested to copy a file from the db directory, that is the same as the /egr/courses/personal/ece410/<username>/synopsys/db directory. 5. Copy the standard cell library you will need for logic synthesis to your directory with the following commands. cd /egr/courses/personal/ece410/resources/iit_stdcells/lib/ami05 cp -R IIT_stdcells_ami05 /egr/courses/personal/ece410/<username>/cadence This completes the environment setup. Tutorial PnR: Place and Route 1Synthesis with Synopsys Design Vision This tutorial will guide you through construction of a multiplexer based on provided VHDL code. The first step is to synthesize the code using the Design Compiler tool from Synopsys. 1. Move to the directory where the multiplexer files are stored. cd /egr/courses/personal/ece410/<username>/synopsys/muxcase 2. Type source $SOFT/synopsys 3. Type design_vision & to start the Design Vision tool. The window in Figure 1 will open. 4. To tell Design Vision that we will be importing a VHDL file, type the following command at the design vision-t> prompt: set hdlin_enable_presto_for_vhdl true Figure 1: Design Vision window with VHDL enabling command. Figure 2: Setup Link and Target Libraries. Note: you should skip this step if a Verilog (the default) file is used. 5. Select File >> Setup. The window in Figure 2 will open. 6. Delete the contents in the Link library, Target library, and Symbol library boxes. 7. Click on the ellipsis (...) next to Link library. 8. Select Add and locate the iit05_stdcells.db file from your db directory. Select OK. 9. Repeat steps 7-8 for Target library. Leave the Symbol library box blank. Select OK to close the setup window. 10. In the Design Vision window, select File >> Analyze. 11. In the window that opens (Fig. 3), click Add. Specify the muxcase.vhd file from your muxcase/source directory. 12. Check the Create new library if it does not exist box. Click OK to close the Analyze Designs window. A window will pop up saying the library already exists. Click OK. 13. Make sure that the bottom of your Design Vision window reports successful compilation as shown in Figure 4. Tutorial PnR: Place and Route 2Figure 3: Analyze Designs window. Figure 5: Elaborate window. Figure 6: Select MUXCASE. 14. In the Design Vision window, select File >> Elaborate to open the window in Figure 5. 15. Drop down the Library menu and select WORK. 16. Check Reanalyze out-of-date libraries. Click OK. 17. In the Design Vision window, select MUXCASE in the Logical Hierarchy sub-window (Fig. 6). 18. Select Hierarchy >> Uniquify >> Hierarchy 19. If you get an error message, click Close. 20. In the Uniquify Hierarchy window click OK. This window may be hidden behind other windows. 21. In the Design Vision window select Design >> Compile Design. 22. Select OK to compile the design and return to the Design Vision window. 23. Select Design >> Check Design. Select OK to check the design. 24. Select File >> Save As and save the file as muxsyn.v in your v directory. 25. Re-save the file as muxsyn.db in your db directory. Be sure to select the DB(db) Format when saving the file. 26. To view the schematic that the Synopsys tools have created from the VHDL file, right-click on MUXCASE in the Logical Hierarchy sub-window and select Schematic View. This is not a necessary design step, but it is interesting to see. 27. Select File >> Exit to exit Design Vision. Figure 4: Design Vision report of successful compilation. Tutorial PnR: Place and Route 3Place & Route with Cadence Silicon Ensemble NOTE: Some students have reported problems running Gnome desktop environment with Silicon Ensemble. It is recommended that you use the Common Desktop Environment. GETTING STARTED 1. Create a folder under /egr/courses/personal/ece410/<username>/se called mux and go to that directory. cd /egr/courses/personal/ece410/<username>/se mkdir mux cd /egr/courses/personal/ece410/<username>/se/mux 2. Type source $SOFT/cadence 3. To launch Silicon Ensemble, type seultra -m=200 & Figure 7: Import LEF into Silicon Ensemble. Figure 8: Add Verilog Source Files. SETUP 4. Select File >> Import >> LEF 5. Select iit05_stdcells.lef from your synopsys/lef directory. 6. Click OK. Figure 7 shows the Silicon Ensemble program window with a message in the bottom feedback window that LEF importing was successful. 7. To add Verilog source files, select File >> Import >> Verilog and click Browse (near Verilog Source Files). 8. In the MultiBrowse window (Fig. 8), select muxsyn.v from your synopsys/v directory and click Add. 9. Also add iit05_stdcells.v.se from the same directory. The trick here is to change the
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