Cadence Troubleshooting Guide A Cadence EDA Tools Help Document Document Contents Introduction Troubleshooting Guide Introduction This document answers/solutions to common questions/problems encountered using the Cadence EDA tools. Troubleshooting Guide: Frequently Asked Questions General My icfb window is frozen. How do I close it? Open an Xterm window and type ps -u username and note the PID for icfb.exe. Execute the command kill -9 PIDno. This will close the cadence session. Delete the lock files if you have any. How do I open the locked file in edit mode? Go the folder in which your design files are stored. Depending on the number of views your design has, you will have folders named schematic, symbol etc. Go to the folder schematic. You might see the files master.tag pc.db prop.xx sch.cd% sch.cd- sch.cdb sch.cdb.cdslck etc. Leave the files master.tag pc.db prop.xx sch.cdb and delete the other files (using rm filename). After this process you should be able to open the file in edit mode. While doing this you should not have any other cadence session accessing the particular file in edit mode (for example you might be accessing the file from home using Xwin). How do I capture images for my lab report? Refer to the Guide to Capturing Images. Library Manager Why can’t I see the default parts libraries in the manager? When you first start Cadence, it creates a new library definition file called “cds.lib” in the directory you launched it from. This links the necessary parts libraries to the Cadence workspace. If the file exists in the launch directory but you aren’t seeing the parts libraries, check to make sure that the following line is in “cds.lib”: INCLUDE /opt/cds/local/cdssetup/cds.lib If necessary, add this statement to the “cds.lib” using the text editor of your choice. To avoid having this problem in the future, always launch Cadence from your class directory, and try not to edit, move or delete the file unless you need to. Why can’t I see any of my own design libraries in the manager? Most likely, you have launched Cadence from a directory that does not contain all of your previous work. A common mistake is to run icfb from your home directory (“/home/<username>/cadence”) and not your class Cadence directory. Make sure you are running icfb from the correct place. Troubleshooting Guide 1Another possibility is that you have copied your design directories to/from another location and the “cds.lib” file that defines the paths to these libraries no longer points to the correct files (or the file is deleted/missing). You will have to manually fix “cds.lib” file by going to Edit->Library Path and enter the library and directory names by hand. Schematic Entry Why do I get a message "Schematic can't be edited. Do you want to open in Read mode?" Whenever Cadence opens a schematic, it creates a lock file. When you exit the Cadence properly by File -> Exit in the Command Interpreter Window, the lock file will be deleted and you will not have any problems in opening the file in edit mode. If by any chance the session is closed abruptly, the lock files will be in your directory which protects the file to be opened in edit mode. Why is there a yellow X “warning” in open area of my schematic after I do a check? It is likely that you have changed the name of a pin in your schematic after having already designed the symbol for it. You will need to change the name of the pin in either the schematic or symbol so that the two match. Why am I getting a warning for some of the wire crossover points in my circuit after I do a check? By default, Cadence flags the intersection of four wires at a solder dot as a warning. As long as you are confident that the wire connections are appropriate, then you may ignore these warnings. Symbolic Entry How do I draw the red selection box around my symbol? Click the “Selection Box” button in the left-hand toolbar of the Symbol Editing window. On the window that pops up, click “Automatic”. This will draw a selection box that bounds the entire symbol within a rectangular selection box. Layout My layout is getting bigger and it has some DRC errors, but I couldn't locate them. Is there an easy way to do it? In the layout editor window go to Verify->Markers->Find. In the form, check the option Zoom to markers and click apply. It will zoom in to all the DRC errors. How do I remove the DRC errors markings in my layout, so that I can edit the layout without any dirty white lines? In the layout editor window, go to Verify->Markers->Delete All and say ok to the window that is popping up. This removes all the DRC error markings. When I instantiate my inverter, I can only see a box with the cellname of the inverter. Why is this happening? This has to do with hierarchical view of the design. When you do the design the topmost cellview (current cellview), it is assigned the number 0 and the other instantiated components are assigned a level above in the hierarchy. The default viewing option is to view the components at a hierarchical level of 0. You can change this by going to Options->Display in the Layout Editor menu and changing the display levels from 0 to 20 (or suitable value of your choice). Troubleshooting Guide 2How do I get the pin names to appear in the layout view? From the menu, select Options->Display. Under display controls, click the box named “Pin Names” on and then click “Apply”. I tried to open a layout and it seems to be invisible. Why can’t I see it? It is possible that no technology library is attached to the cell and that no valid layers are defined (confirm by looking at the LSW window). Attach a tech library to the library where the cell is located by opening the Library manager, right click on the library name, select “Attach Tech Library”, and select the appropriate tech library from the drop-down menu (“AMI 0.60u C5N” for ECE410) Extracted View How do I see the parasitic capacitors in the extracted view? The default setup doesn't extract the parasitic capacitance in the layout. You have to run the command “NCSU_parasiticCapIgnoreThreshold=1e-18” in the command interpreter window before extracting the cell view. Now if you open the extracted view you can see the extracted parasitic capacitors. Press “shift+ f” to see all the transistors in the extracted view. Layout-versus-Schematic (LVS) Why do I get a message
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